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PDF MTV24LC08 Data sheet ( Hoja de datos )
| Número de pieza | MTV24LC08 | |
| Descripción | (MTV24C08 / MTV24LC08) 2-Wire 8912-Bit Serial CMOS EEPROM | |
| Fabricantes | ETC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MTV24LC08 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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MYSON
TECHNOLOGY
MTV24C08/
24LC08
(Preliminary)
2-Wire 8912-Bit Serial CMOS EEPROM
FEATURES
• State- of- the- Art Architecture
- Non-volatile data storage
- Standard Voltage and Low Voltage Operation
5.0(Vcc = 4.5V to 5.5V) for MTV24C08
3.0(Vcc = 2.7V to 5.5V) for 24LC08
• 2 wire I2C serial interface
- Provides bidirectional data transfer protocol
• 16-byte page write mode
- Minimizes total write time per word
• Self-timed write-cycle(including auto-erase)
• Durable and Reliable
- 10 years data retention after 1000K write/erase cycles
- Minimum of 1,000,000 write/erase cycles per word
- Unlimited read cycles
- ESD protection
• Low standby current
GENERAL DESCRIPTION
The MTV24C08/24LC08 is a low cost, non-volatile, 4096-bit serial EEPROM with enhanced security device
and conforms to all specifications in I2C 2 wire protocol. The whole memory can be disabled (Write
Protected) by connecting the WP pin to Vcc. This section of memory then becomes unalterable unless WP
is switched to Vss. It is enhanced with security function. Every word of the memory has a programmable
security bit to permit whether it can be altered or not. The MTV24C08/24LC08's communication protocol
uses CLOCK(SCL) and DATA I/O(SDA) lines to synchronously clock data between the master (for example
a microcomputer)and the slave EEPROM devices(s) .In addition, the bus structure allows for a maximum of
16K of EEPROM memory. This supports the family in 2K, 4K, 8K, 16K devices, allowing the user to
configure the memory as the application requires with any combination of EEPROMs (not to exceed 16K).
MTV EEPROMs are designed and tested for application requiring high endurance, high reliability, and low
power consumption.
This datasheet contains new product information. Analog Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
MTV24C08/24LC08 Revision.1.0 11/03/1999
1/15
1 page  
MYSON
TECHNOLOGY
MTV24C08/
24LC08
(Preliminary)
WRITE OPERATIONS
Byte Write
Following the start signal from the master, the slave address is placed onto the bus by the
master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the ninth clock cycle.
Therefore the next byte transmitted by the master is the word address and will be written into the address
pointer of the MTV24C08/24LC08. After receiving another acknowledge signal from the MTV24C08/24LC08
the master device will transmit the data word to be written into the addressed memory location. The
MTV24C08/24LC08 acknowledges again and the master generates a stop condition. This initiates the
internal write cycle, and during this period the MTV24C08/24LC08 will not generate acknowledge signals.
(Shown in Figure 4)
Page Write
The write control byte, word address and the first data byte are transmitted to the MTV24C08/24LC08 in the
same way as in a byte write. But instead of generating a stop condition the master transmit up to 16 data
bytes to the MTV24C08/24LC08 which are temporarily stored in the on-chip page buffer and will be written
into the memory after the master has transmitted a stop condition. After the receipt of each byte, the two
lower order address pointer bits are internally incremented by one. The higher order six bits of the word
address remains constant. If the master should transmit more than 16 bytes prior to generating the stop
condition, the address counter will roll over and the previously received data will be overwritten. As with the
byte write operation, once the stop condition is received an internal write cycle will begin. (Shown in Figure
5).
Acknowledge Polling
Since the device will not acknowledge during a write cycle , this can be used to determine when the cycle is
complete (this feature can be used to maximize bus throughout). Once the stop condition for a write
command has been issued from the master, the device initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master sending a start condition followed by the control byte
for a write command (R/W = 0). If the device is still busy with the write cycle , then no ACK will returned. If
the cycle is complete then the device will return the ACK and the master can then proceed with the next
read or write commands.
Write Protection
Programming will not take place if the WP pin of the MTV24C08/24LC08 is connected to Vcc. The
MTV24C08/24LC08 will accept slave and byte addresses; but if the memory accessed is write protected by
the WP pin, the MTV24C08/24LC08 will not generate an acknowledge after the first byte of data has been
received, and thus the programming cycle will not be started when the stop condition is asserted.
READ OPERATIONS
Read operations are initiated in the same way as write operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types of read operations: current address read, random
read, and sequential read.
MTV24C08/24LC08 Revision.1.0 11/03/1999
5/15
5 Page 
MYSON
TECHNOLOGY
MTV24C08/
24LC08
(Preliminary)
BUS ACTIVITY
MASTER
S
T
A
R
T
SDA LINE
s
BUS ACTIVITY
SLAVE
SLAVE
ADDRESS
A
C
K
DATA
S
T
O
P
P
Figure 6. Current Address Read for Data
BUS ACTIVITY
MASTER
S
T
A
R
T
SDA LINE S
SLAVE
ADDRESS
BYTE
ADDRESS n
S
T SLAVE
A ADDRESS
R
T
S
BUS ACTIVITY
SLAVE
AA
CC
KK
A
C
K
DATA n
Figure 7. Random Read for Data
S
T
O
P
P
BUS ACTIVITY
MASTER
S
T
A
R
T
SDA LINE S
BUS ACTIVITY
SLAVE
SLAVE
ADDRESS
A
C
K
AA
CC
KK
DATA n
DATA n+1
DATA n+x
S
T
O
P
P
A
C
K
Figure 8. Sequential Read for Data
11/15
MTV24C08/24LC08 Revision.1.0 11/03/1999
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet MTV24LC08.PDF ] | |
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