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PDF 71M6513 Data sheet ( Hoja de datos )
| Número de pieza | 71M6513 | |
| Descripción | Power Meter IC | |
| Fabricantes | TDK | |
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GENERAL DESCRIPTION
71M6513/71M6513H
Power Meter IC
PRELIMINARY DATASHEET
SEPTEMBER 2004
FEATURES
The TDK 71M6513 is a highly integrated SOC with an MPU core,
RTC, FLASH and LCD driver. TDK’s patent pending Single Con-
verter Technology with a 21-bit delta-sigma ADC, 6 analog
inputs, digital temperature compensation, precision voltage
reference and 32-bit computation engine support a wide range of
polyphase metering applications with very few low cost external
components. A 32kHz crystal timebase for the entire system and
internal battery backup support for RAM and RTC further reduce
system cost.
Maximum design flexibility is supported with multiple UARTs, I2C,
power fail comparator, 5V LCD charge pump, up to 22 DIO pins and
in system programmable FLASH which can be updated with data or
application code in operation. Easy conversion to ROM offers un-
precedented cost structure for high volume applications. The device
is offered in high (0.1%) and low (0.5%) accuracy versions for multi-
function residential/commercial meter applications requiring multiple
voltage/current inputs, larger LCD or DIO features.
A complete array of ICE and development tools, programming
libraries and reference designs enable rapid development and
certification of meters that meet most demanding world wide
electricity metering standards.
LIVE
NEUT
LIVE
CT /COIL
LIVE
LOAD
POWER SUPPLY
AMR
IR
POWER
FAULT
etc.
CONVERTER
IA
VA
IB
VB
IC
VC
VOLTAGE REF
VREF
VBIAS
SERIAL PORTS
TX
RX
SENSE RX
DRIVE TX
COMPARATOR
V1
V2
V3
V3.3A V3.3D GNDA GNDD
5V BOOST
TDK
VDRV
71M6513 REGULATOR
VBAT
V2.5
TEMP
SENSOR
LCD DRIVER
DIO, PULSE
RAM
COMPUTE
ENGINE
VLCD
COM0..3
SEG0..23
SEG 24..27
DIO 4..11
FLASH/
ROM
SEG 32..41
DIO 12..21
MPU
RTC
TIMERS
ICE
DIO 0..3
OSC/PLL
XIN
XOUT
BATTERY
3/5V LCD
88.88.8888
MISC
EEPROM
32 kHz
< 0.1% Wh accuracy over 2000:1
range (71M6513H version)
< 0.5% Wh accuracy over 2000:1
range (71M6513 version)
Exceeds IEC62053 / ANSIC12.20.
Voltage reference < 10ppm/°C spec
(71M6513H version), <50ppm/°C
(71M6513 version)
Six sensor inputs - VDD referenced
Four quadrant metering
Voltage angles -- phase sequence
Digital temperature compensation
21-bit delta-sigma ADC
Independent 32bit compute engine
Low jitter Wh/ VARh pulse outputs
40-70Hz line frequency range
Phase compensation (±7°)
Battery Backup for RAM and RTC
29mW @3.3V, 7.2µW back up.
Flash memory option with security
8-bit microcontroller (80515) - 1 clock
cycle per instruction
Integrated ICE for MPU debug
LCD driver (≤168 pixels)
High speed SSI serial output
RTC for time of use functions
Two Event counter/timers
Watchdog timer
Power fail monitor
Up to 22 general purpose I/O pins
64kB Flash or ROM
7kB RAM
Two UARTs for IR and AMR
Third software UART via DIO pins
100-lead Exposed Pad LQFP
package (epLQFP)
Rev 2.9
PRELIMINARY DATA SHEET
Page: 1 of 56
1 page  
71M6513/71M6513H
Power Meter IC
PRELIMINARY DATASHEET
SEPTEMBER 2004
Figure 1: IC Functional block diagram
VREF VBIAS
V3P3A GNDA GNDA
IA
VA
IB
VB
IC
VC
XIN
XOUT
CKTEST
TEST
TX
RX
OPT_TX
OPT_RX
V1
V2
V3
MUX
VBIAS
V3
TEMP
MUX
MUX
CTRL
EQU
MUX_ALT
MUX_DIV
VREF
CHOP_EN
VREF_DIS
CK32
∆Σ ADC
CONVERTER
V3P3A
-
+
VREF
FIR
FILTER
FIR_LEN
VOLTAGE
BOOST
LCD_IBST
LCD_BSTEN
V2P5NV
GNDD
V3P3D
VOLT
REG
OSC
(32KHz)
OSC_DIS
V2P5NV
RTCLK (32KHz)
MCK
PLL
CKOUT_EN
4.9MHz
CK_GEN
ECK_DIS
MPU_DIV
CK_EN
MUX_SYNC STRT
TEST
MODE
CKCE
4.9MHz
SCALE_TAGS
HW_TAGS
CE
32 bit Compute
Engine
WPULSE
VARPULSE
RTM
DATA
00-FF
CKFIR
4.9MHz
CE DATA
RAM
(1KB)
MUX
MEMORY
SHARE
0.1V
2.5V to logic
V2P5
SSI
CTRL
LCD DAC
LCD_MODE
LCD_FS
LCD_EN
LCD DISPLAY
DRIVER
CE
CONTROL
EQU
PRE_SAMPS
SUM_CYCLES
RTM_EN
CE_EN
PROG
000-7FF
1000-13FF
CE PROG
RAM
(4KB)
CE_RUN
CE_LOAD
WPULSE
VARPULSE
3000-3FFF
LCD_NUM
LCD_MODE
LCD_CLK
LCD_EN
DIGITAL I/O
DIO_EEX
PULSEV/W
DIO_IN
DIO_OUT
LCD_NUM
DIO_GP
UART
CKMPU
<4.9MHz
MPU
(8051)
SDCK
SDOUT
SDIN
OPTICAL
OPT_TXDIS
VREF
POWER FAULT
COMP_STAT
COMP_INT
WAKE
FAULTZ
MPU_RSTZ
V3P3
EEPROM
INTERFACE
DATA
0000-FFFF
PROG
0000-FFFF
2000-20FF
0000-07FF
V2P5NV
0000-FFFF
EMULATOR
PORT
RTC
RTC_HOLD
RTC_SET
RTCLK
V2P5NV
CONFIG
RAM
CONFIGURATION
PARAMETERS
MPU XRAM
(2KB)
FLASH
(64KB)
EERDSLOW
EEWRSLOW
XFER_BUSY
CE_BUSY
RTCLK
PULSE_OUT
CK_MPU
CK_10M
MUX_SYNC
OPTRX
V3_OK
V2_OK
WDTR_EN
RTM
VBIAS
PLL_2.5V
IBIAS
DGND
DMUX
F
E
D
C
B
A
DIGITAL
9
8
7
6
5
4
3
2
ANALOG
1
0
TMUX
VDRV
GNDD
V3P3D
VBAT
GNDD
GNDD
V2P5
VLCD
COM0..3
SEG6/SRDY
SEG0..2, SEG3/SCLK,
SEG4/SSDATA,
SEG5/SFR, SEG7..19
SEG20..23
SEG24/DIO4 ..
SEG27/DIO7
SEG28/DIO8 ..
SEG31/DIO11
SEG32/DIO12 ..
SEG41/DIO21
DIO_0..3
TMUXOUT
RESETZ
E_RXTX
E_TCLK
E_RST
(Open Drain)
E_ISYNC/BRKRQ
E_TBUS[3:0]
4
September 17, 2004
Rev 2.9
PRELIMINARY DATA SHEET
Page: 5 of 56
5 Page 
71M6513/71M6513H
Power Meter IC
PRELIMINARY DATASHEET
SEPTEMBER 2004
The CE contains a Real Time Monitor (RTM) which can be programmed through the UART to monitor four
selectable CE RAM locations at full sample rate. The four monitored locations are serially output to the
TMUXOUT pin via the digital output multiplexer at the beginning of each CE code pass. The RTM can be
enabled and disabled with RTM_EN. The RTM output is clocked by CKTEST. Each RTM word is clocked out in
35 cycles and contains a leading flag bit. Figure 2 illustrates the RTM output format. RTM is low when not in use.
Figure 2: RTM Output Format
CK32
MUX_SYNC
CKTEST
TMUXOUT/RTM
FLAG
RTMDATA0 (32 bits)
RTMDATA1 (32 bits)
RTMDATA2 (32 bits)
RTMDATA3 (32 bits)
0 1 30 31
FLAG
0 1 30 31
FLAG
0 1 30 31
FLAG
0 1 30 31
Clock Generator: The CE clock frequency is always CK32 * 150. The MPU clock frequency is determined by
MPU_DIV and can be CE*2-MPU_DIV Hz where MPU_DIV varies from 0 to 7. This makes the MPU clock scalable
from 4.9152MHz down to 38.4kHz. CK32 is the 32kHz clock. The circuit also generates a 2x MPU clock for use
by the emulator. This clock is not generated when ECK_DIS is asserted by the emulator.
CE RAM: The CE data RAM can be accessed by the FIR filter block, the RTM, the CE, and the MPU. Assigned
time slots are reserved for FIR, RTM, and MPU, respectively, such that memory accesses to CE_RAM do not
collide. Holding registers are used to convert 8-bit wide MPU data to/from 32-bit wide CE_RAM data, and wait
states are inserted as needed, depending on the frequency of CKMPU. RTM data is read from the CE RAM
locations specified by RTM0, RTM1, RTM2, and RTM3 after the rise of MUX_SYNC.
CE PRAM: The CE program RAM is loaded at boot time by the MPU and then accessed as necessary by the
CE. Each CE instruction word is 2 bytes long. PRAM memory size is 2048 words. The CE program counter
begins a pass through the CE code each time multiplexer state 0 begins. The code pass ends when a HALT
instruction is executed. For proper operation, the code pass must be completed before the MUX_SYNC signal
rises.
CE Communication with MPU: The CE outputs two signals to the MPU: CE_BUSY and XFER_BUSY. These
are connected to the MPU interrupt service inputs. CE_BUSY indicates that the CE is actively processing data.
This signal will occur once every multiplexer frame. XFER_BUSY indicates that the CE is updating to the Output
Rev 2.9
PRELIMINARY DATA SHEET
Page: 11 of 56
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 71M6513.PDF ] | |
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