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PDF N80C188EBxx Data sheet ( Hoja de datos )
| Número de pieza | N80C188EBxx | |
| Descripción | (N80C186EBxx / TN80C188EBxx) 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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80C186EB 80C188EB AND 80L186EB 80L188EB
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
X Full Static Operation
X True CMOS Inputs and Outputs
Y Integrated Feature Set
Low-Power Static CPU Core
Two Independent UARTs each with
an Integral Baud Rate Generator
Two 8-Bit Multiplexed I O Ports
Programmable Interrupt Controller
Three Programmable 16-Bit
Timer Counters
Clock Generator
Ten Programmable Chip Selects with
Integral Wait-State Generator
Memory Refresh Control Unit
System Level Testing Support (ONCE
Mode)
Y Direct Addressing Capability to 1 Mbyte
Memory and 64 Kbyte I O
Y Speed Versions Available (5V)
25 MHz (80C186EB25 80C188EB25)
20 MHz (80C186EB20 80C188EB20)
13 MHz (80C186EB13 80C188EB13)
Y Available in Extended Temperature
Range (b40 C to a85 C)
Y Speed Versions Available (3V)
16 MHz (80L186EB16 80L188EB16)
13 MHz (80L186EB13 80L188EB13)
8 MHz (80L186EB8 80L188EB8)
Y Low-Power Operating Modes
Idle Mode Freezes CPU Clocks but
keeps Peripherals Active
Powerdown Mode Freezes All
Internal Clocks
Y Supports 80C187 Numeric Coprocessor
Interface (80C186EB PLCC Only)
Y Available In
80-Pin Quad Flat Pack (QFP)
84-Pin Plastic Leaded Chip Carrier
(PLCC)
80-Pin Shrink Quad Flat Pack (SQFP)
The 80C186EB is a second generation CHMOS High-Integration microprocessor It has features that are new
to the 80C186 family and include a STATIC CPU core an enhanced Chip Select decode unit two independent
Serial Channels I O ports and the capability of Idle or Powerdown low power modes
272433 – 1
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
October 1995
Order Number 272433-004
COPYRIGHT INTEL CORPORATION 1995
1
1 page  
80C186EB 80C188EB 80L186EB 80L188EB
272433 – 4
272433 – 3
(A) Crystal Connection
(B) Clock Connection
NOTE
The L1C1 network is only required when using a third-
overtone crystal
Figure 2 Clock Configurations
The following parameters are recommended when
choosing a crystal
Temperature Range
Application Specific
ESR (Equivalent Series Resistance)
40X max
C0 (Shunt Capacitance of Crystal)
7 0 pF max
CL (Load Capacitance)
Drive Level
20 pF g 2 pF
1 mW max
80C186EB PERIPHERAL
ARCHITECTURE
The 80C186EB has integrated several common sys-
tem peripherals with a CPU core to create a com-
pact yet powerful system The integrated peripher-
als are designed to be flexible and provide logical
interconnections between supporting units (e g the
interrupt control unit supports interrupt requests
from the timer counters or serial channels)
The list of integrated peripherals includes
7-Input Interrupt Control Unit
3-Channel Timer Counter Unit
2-Channel Serial Communications Unit
10-Output Chip-Select Unit
I O Port Unit
Refresh Control Unit
Power Management Unit
The registers associated with each integrated peri-
heral are contained within a 128 x 16 register file
called the Peripheral Control Block (PCB) The PCB
can be located in either memory or I O space on
any 256 Byte address boundary
Figure 3 provides a list of the registers associated
with the PCB The Register Bit Summary at the end
of this specification individually lists all of the regis-
ters and identifies each of their programming attri-
butes
Interrupt Control Unit
The 80C186EB can receive interrupts from a num-
ber of sources both internal and external The inter-
rupt control unit serves to merge these requests on
a priority basis for individual service by the CPU
Each interrupt source can be independently masked
by the Interrupt Control Unit (ICU) or all interrupts
can be globally masked by the CPU
Internal interrupt sources include the Timers and Se-
rial channel 0 External interrupt sources come from
the five input pins INT4 0 The NMI interrupt pin is
not controlled by the ICU and is passed directly to
the CPU Although the Timer and Serial channel
each have only one request input to the ICU sepa-
rate vector types are generated to service individual
interrupts within the Timer and Serial channel units
Timer Counter Unit
The 80C186EB Timer Counter Unit (TCU) provides
three 16-bit programmable timers Two of these are
highly flexible and are connected to external pins for
control or clocking A third timer is not connected to
any external pins and can only be clocked internally
However it can be used to clock the other two timer
channels The TCU can be used to count external
events time external events generate non-repeti-
tive waveforms generate timed interrupts etc
5
5
5 Page 
80C186EB 80C188EB 80L186EB 80L188EB
Table 3 Pin Descriptions (Continued)
Pin
Name
Pin Input Output
Type Type States
Description
A18 16
A19 ONCE
(A15 A8)
(A18 16)
(A19 ONCE)
IO
A(L) H(Z) These pins provide multiplexed Address during the address
R(WH) phase of the bus cycle Address bits 16 through 19 are presented
P(X) on these pins and can be latched using ALE These pins are
driven to a logic 0 during the data phase of the bus cycle On the
80C188EB A15 – A8 provide valid address information for the
entire bus cycle During a processor reset (RESIN active) A19
ONCE is used to enable ONCE mode A18 16 must not be driven
low during reset or improper operation may result
S2 0
O
H(Z)
R(Z)
P(1)
Bus cycle Status are encoded on these pins to provide bus
transaction information S2 0 are encoded as follows
S2 S1 S0
Bus Cycle Initiated
0 0 0 Interrupt Acknowledge
0 0 1 Read I O
0 1 0 Write I O
0 1 1 Processor HALT
1 0 0 Queue Instruction Fetch
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive (no bus activity)
ALE O
H(0) Address Latch Enable output is used to strobe address
R(0) information into a transparent type latch during the address phase
P(0) of the bus cycle
BHE
(RFSH)
O
H(Z)
R(Z)
P(X)
Byte High Enable output to indicate that the bus cycle in progress
is transferring data over the upper half of the data bus BHE and
A0 have the following logical encoding
A0 BHE Encoding (for the 80C186EB 80L186EB only)
0 0 Word Transfer
0 1 Even Byte Transfer
1 0 Odd Byte Transfer
1 1 Refresh Operation
On the 80C188EB 80L188EB RFSH is asserted low to indicate a
refresh bus cycle
RD O H(Z) ReaD output signals that the accessed memory or I O device
R(Z) must drive data information onto the data bus
P(1)
WR O H(Z) WRite output signals that data available on the data bus are to be
R(Z) written into the accessed memory or I O device
P(1)
READY
I A(L)
S(L)
READY input to signal the completion of a bus cycle READY
must be active to terminate any bus cycle unless it is ignored by
correctly programming the Chip-Select Unit
DEN
O
H(Z)
R(Z)
P(1)
Data ENable output to control the enable of bi-directional
transceivers in a buffered system DEN is active only when data is
to be transferred on the bus
NOTE
Pin names in parentheses apply to the 80C188EB 80L188EB
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