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PDF MTV030 Data sheet ( Hoja de datos )
| Número de pieza | MTV030 | |
| Descripción | On-Screen Display with Auto-Sizing Controller | |
| Fabricantes | Myson | |
| Logotipo |  |
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MYSON
TECHNOLOGY
MTV030
On-Screen Display with Auto-Sizing Controller
FEATURES
• Horizontal SYNC input up to 150 KHz.
• On-chip PLL circuitry up to 150 MHz.
• Minimum timing measurement among HFLB, VFLB, RIN,
GIN and BIN for auto sizing.
• Full screen self-test pattern generator.
• Programmable Hor. resolutions up to 1524 dots per line.
• Full-screen display consists of 15 (rows) by 30 (columns)
• Two font size 12x16 or 12x18 dot matrix per character.
• True totally 512 mask ROM fonts including 496 standard
fonts and 16 multi-color fonts.
• Double character height and/or width control.
• Programmable positioning for display screen center.
• Character bordering, shadowing and blinking effect.
• Programmable character height (18 to 71 lines) control.
• Row to row spacing control to avoid expansion distortion.
• 4 programmable windows with multi-level operation.
• Shadowing on windows with programmable shadow
width/height/color.
• Programmable adaptive approach to handle H, V sync
collision automatically by hardware.
• Software clears bit for full-screen erasing.
• Fade-in/fade-out or blending-in/blending-out effects.
• 5-channel/8-bit PWM D/A converter output.
• Compatible with SPI bus or I2C interface with slave
address 7AH/7BH (slave address is mask option).
• 16-pin, 20-pin or 24-pin PDIP package.
GENERAL DESCRIPTION
MTV030 is designed for monitor applications to display
built-in characters or fonts onto monitor screens. The dis-
play operation occurs by transferring data and control infor-
mation from the micro-controller to RAM through a serial
data interface. It can execute full-screen display automati-
cally, as well as specific functions such as character back-
ground, bordering, shadowing, blinking, double height and
width, font by font color control, frame positioning, frame
size control by character height and row-to-row spacing,
horizontal display resolution, full-screen erasing, fade-in/
fade-out effect, windowing effect, shadowing on window
and full-screen self-test pattern generator.
MTV030 provides true 512 fonts including 496 standard
fonts and 16 multi-color fonts and 2 font sizes, 12x16 or
12x18 for more efficacious applications. So each one of the
512 fonts can be displayed at the same time. The full OSD
menu is formed by 15 rows x 30 columns, which can be
positioned anywhere on the monitor screen by changing
vertical or horizontal delay.
The auto sizing video measurement module measure
the timing relationship among HFLB, VFLB, and R, G, BIN
at the speed related to the OSD resolution. MCU can get
the measurement data, active video, front porth and back
porth, through I2C bus read/write operation to keep the
appropriate display size and center.
BLOCK DIAGRAM
SSB
SCK
SDA
VFLB
HFLB
RP
VCO
PWM0
PWM1
PWM2
PWM3
PWM4
SERIAL DATA
INTERFACE
8DATA
9ROW, COL
ACK
ARWDB
HDREN
VDREN
NROW
ADDRESS BUS
ADMINISTRATOR
5 RCADDR
9 DADDR
9 FONTADDR
5 WINADDR
5 PWMADDR
VSP
CH 7
CHS
VERTD 8
VERTICAL
DISPLAY
CONTROL
5 LPN
NROW
VDREN
HORIZONTAL
ARWDB
HSP HORD 8 DISPLAY CONTROL HDREN
PHASE LOCK LOOP VCLKX
PWM D/A
CONVERTER
8 DATA
POWER ON RESET PRB
DATA 8
CWS
CHS
DISPLAY & ROW
CONTROL
REGISTERS
LUMAR
LUMAG
LUMAB
BLINK
8 CRADDR
DATA 8
LPN 5
CWS
VCLKS
CHARACTER ROM
LUMINANCE &
BORDGER
GENERATOR
LUMA
BORDER
DATA 8
8 VERTD
8 HORD
7 CH
WINDOWS &
FRAME
CONTROL
BSEN
SHADOW
OSDENB
HSP
VSP
LUMAR
LUMAG
LUMAB
BLINK
VCLKX
COLOUR
ENCODER
DATA 8 AUTO SIZING
MEASUREMENT
VDD
VSS
VDDA
VSSA
ROUT
GOUT
BOUT
FBKG
HTONE
RIN
GIN
BIN
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
1/21 MTV030 Revision 1.0 10/15/1999
1 page  
MYSON
TECHNOLOGY
MTV030
In the I2C read mode, 10 bytes of auto sizing video measurement data will be output directly from byte 0 to
byte 9 and continues with dummy data until stop condition occurred when I2C R/W bit is set to “1”.
Each arbitrary length of data packet consists of 3 portions viz, Row address (R), Column address (C), and
Display data (D). Format (a) is suitable for updating small amount of data which will be allocated with different
row address and column address. Format (b) is recommended for updating data that has same row address
but different column address. Massive data updating or full screen data change should use format (c) to
increase transmission efficiency. The row and column address will be incremented automatically when the for-
mat (c) is applied. Furthermore, the undefined locations in display or fonts RAM should be filled with dummy
data.
TABLE 1. The configuration of transmission formats.
Address b7 b6 b5 b4 b3 b2 b1 b0 Format
Row
1 0 0 R4 R3 R2 R1 R0
Address Bytes Columnab
of Display Reg. Columnc
0
0
0 D8 C4 C3 C2 C1 C0
1 D8 C4 C3 C2 C1 C0
Data
D7 D6 D5 D4 D3 D2 D1 D0
Row
1 0 1 R4 R3 R2 R1 R0
Attribute Bytes Columnab 0 0 x C4 C3 C2 C1 C0
of Display Reg. Columnc 0 1 x C4 C3 C2 C1 C0
Data
D7 D6 D5 D4 D3 D2 D1 D0
a,b,c
a,b
c
a,b,c
a,b,c
a,b
c
a,b,c
There are 2 types of data should be accessed through the serial data interface, one is ADDRESS bytes of dis-
play registers, and other is ATTRIBUTE bytes of display registers, the protocol are same for all except the bit5
of row address and the bit5 of column address. The MSB(b7) is used to distinguish row and column
addresses when transferring data from external controller. The bit6 of column address is used to differentiate
the column address for format (a), (b) and format (c) respectively. Bit5 of row address for display register is
used to distinguish ADDRESS byte when it is set to "0" and ATTRIBUTE byte when it is set to "1". And at
address bytes, bit5 of column address is the MSB (bit8) and data bytes are the 8 LSB (bit7~bit0) of dis-
play fonts address to save half MCU memory for true 512 fonts. So each one of the 512 fonts can be dis-
played at the same time. See Table 1. And for format (c), since D8 is filled while program column address of
address bytes, the continued data will be the same bank of upper 256 fonts or lower 256 fonts until program
column address of address bytes again.
The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format
(a) and (c), but not from format (c) back to format (a) and (b). The alternation between transmission formats is
configured as the state diagram shown in Figure 3.
3.2 Address bus administrator
The administrator manages bus address arbitration of internal registers or user fonts RAM during external
data write in. The external data write through serial data interface to registers must be synchronized by inter-
nal display timing. In addition, the administrator also provides automatic increment to address bus when exter-
nal write using format (c).
3.3 Vertical display control
The vertical display control can generates different vertical display sizes for most display standards in current
monitors. The vertical display size is calculated with the information of double character height bit(CHS), verti-
5/21 MTV030 Revision 1.0 10/15/1999
5 Page 
MYSON
TECHNOLOGY
MTV030
tents of CH4-CH0 is greater than or equal to 18, it will be regarded as equal to 17. See Table 2
and Table 3 for detail description of this operation.
b7 b6 b5 b4 b3 b2 b1 b0
Column 15
-
MSB
HORR
LSB
HORR - Specify the resolution of a horizontal display line, and the increment of each step is 12 dots. That is,
the pixels' number per H line equal to HORR*12. It is recommended that HORR should be greater
than or equal to 36 and smaller than 150M / (Hfreq*12). The initial value is 40 after power up.
b7 b6 b5 b4 b3 b2 b1 b0
Column 16 - - -
MSB
RSPACE
LSB
RSPACE - Define the row to row spacing in unit of horizontal line. That is, extra RSPACE horizontal lines will
be appended below each display row, and the maximum space is 31 lines. The initial value is 0
after power up.
b7 b6
b5 b4 b3
b2
b1 b0
Column 17 OSDEN BSEN SHADOW FBEN BLEND WENCLR RAMCLR FBKGC
OSDEN - Activate the OSD operation when this bit is set to "1". The initial value is 0 after power up.
BSEN - Enable the bordering and shadowing effect.
SHADOW - Bordering and shadowing effect select bit. Activate the shadowing effect if this bit is set, otherwise
the bordering is chosen.
FBEN - Enable the fade-in/fade-out and blending-in/blending-out effect when OSD is turned on from off state
or vice verca.
BLEND - Fade-in/fade-out and blending-in/blending-out effect select bit. Activate the blending-in/blending-out
function if this bit is set, otherwise the fade-in/fade-out function is chosen. These function roughly
takes about 0.5 second to fully display the whole menu or to disappear completely.
WENCLR - Clear all WEN bits of window control registers when this bit is set to "1". The initial value is 0 after
power up.
RAMCLR - Clear all ADDRESS bytes, BGR, BGG, BGB and BLINK bits of display registers when this bit is set
to "1". The initial value is 0 after power up.
FBKGC - Define the output configuration for FBKG pin. When it is set to "0", the FBKG outputs high during the
displaying of characters or windows, otherwise, it outputs high only during the displaying of charac-
ter.
B7
Column 18 TRIC
b6
FSS
b5 b4 b3
VMEN SELVCL HSP
b2 b1 b0
VSP VCO1 VCO0
TRIC - Define the driving state of output pins ROUT, GOUT, BOUT and FBKG when OSD is disabled. That is,
while OSD is disabled, these four pins will drive low if this bit is set to 1, otherwise these four pins are
in high impedance state. The initial value is 0 after power up.
11/21
MTV030 Revision 1.0 10/15/1999
11 Page | ||
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| PDF Descargar | [ Datasheet MTV030.PDF ] | |
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