MTV016 Datasheet PDF - Myson
| Part Number | MTV016 | |
| Description | Enhanced On-Screen-Display Controller | |
| Manufacturers | Myson | |
| Logo |  |
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MYSON
TECHNOLOGY
MTV016
Enhanced On-Screen-Display Controller
FEATURES
• Horizontal SYNC input up to 100 KHz.
• On-chip PLL circuitry up to a 90 MHz pixel rate for multi-SYNC operation.
• Programmable horizontal resolutions up to 1524 dots per display row.
• 538-byte display registers to control full screen display.
• Full screen display consists of 10 (rows) by 24 (columns) characters.
• 12 x 18 dot matrix per character.
• 128 built-in characters and graphic symbols, and character by character color selection.
• Maximum of 8 colors selectable per display row.
• Double character height and/or width control.
• Programmable positioning for display screen center.
• Bordering and shadowing effect for display.
• Programmable vertical character height (18 to 71 lines) for multi-SYNC operation.
• 4 programmable background windows with multi-level windowing effect.
• Software clear function for display frame buffer.
• HSYNC and VSYNC input polarity selectable.
• Auto detection for input edge distortion between HSYNC and VSYNC inputs.
• Half tone and fast blanking output.
• Software force blank function for display frame.
• Compatible with both SPI bus and I2C interface through pin selection.
• 16-pin PDIP package.
GENERAL DESCRIPTION
MTV016 is designed for use in monitor applications to display the built-in characters or symbols onto a
monitor screen. The display operation occurs by transferring data and control information in the micro-
controller to RAM through a serial data interface. It can execute a full screen display automatically and
specific functions such as character bordering, shadowing, double height and width, font by font color
control, frame positioning, frame size control by character height and horizontal display resolution, and
windowing effect.
BLOCK DIAGRAM
SSB
8 DATA
SCK
SERIAL DATA DAEN
INTERFACE
2 RAEN,CAEN
SDA
ARWDB
HDREN
VDREN
NROW
ADDRESS BUS
ADMINISTRATOR
5 RCADDR
9 DADDR
5 WADDR
VFLB VERTICAL 5 LPN
VSP
CH 7
CHS
VERTD 8
DISPLAY
CONTROL
NROW
VDREN
DATA 5
CWS
CHS
DISPLAY & ROW
CONTROL
REGISTERS
CCS0
CCS1
BLINK
7 CRADDR
LPN 5
CWS
VCLKS
CHARACTER ROM
LUMINANCE &
BORDGER
GENERATOR
LUMA
BORDER
DATA 8
8 VERTD
8 HORD
7 CH
WINDOWS &
FRAME
CONTROL
BSEN
SHADOW
OSDENB
HSP
VSP
VDD
VSS
VDDA
VSSA
HFLB
HORIZONTAL
ARWDB
HSP HORD 7 DISPLAY CONTROL HDREN
RP
PHASE LOCK LOOP VCLKX
VCO
CCS0
CCS1
BLINK
VCLKX
COLOUR
ENCODER
ROUT
GOUT
BOUT
FBKG
HTONE
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
1/11
MTV016 Revision 2.0 01/01/1999
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MYSON
TECHNOLOGY
MTV016
character line displays is shown in Tables 2 and 3. The programmable vertical size range is 180 lines to
a maximum of 1420 lines.
The vertical display center for a full screen display may be figured out according to the information of the
vertical starting position register (VERTD) and VFLB input. The vertical delay starting from the leading
edge of VFLB is calculated using the following equation:
vertical delay time = (VERTD * 4 + 1) * H
H = one horizontal line display time
Table 2. Repeat Line Weight of Character
CH6 - CH0
Repeat Line Weight
CH6,CH5=11
+18*3
CH6,CH5=10
+18*2
CH6,CH5=0x
+18
CH4=1
+16
CH3=1
+8
CH2=1
+4
CH1=1
+2
CH0=1
+1
Table 3. Repeat Line Number of Character
Repeat Line
Repeat Line #
Weight
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
+1 - - - - - - - - v - - - - - - - - -
+2 - - - - v - - - - - - - v - - - - -
+4 - - v - - - v - - - v - - - v - - -
+8 - v - v - v - v - v - v - v - v - -
+16 - v v v v v v v v v v v v v v v v -
+17 v v v v v v v v v v v v v v v v v -
+18 v v v v v v v v v v v v v v v v v v
Note:" v " means the nth line in the character would be repeated once, while " - " means the nth line in the character would not be
repeated.
3.4 Horizontal Display Control
The horizontal display control is used to generate control timing for horizontal displays based on double
character width bit (CWS), horizontal positioning register (HORD), horizontal resolution register (HORR)
and HFLB input. A horizontal display line consists of (HORR*12) dots, including 288 dots for 24 display
characters; the remaining dots are for a blank region. The horizontal delay starting from the HFLB
leading edge is calculated using the following equation:
horizontal delay time = (HORD * 6 + 49) * P - phase error detection pulse width
P = one pixel display time = one horizontal line display time / (HORR*12)
3.5 Phase Lock Loop (PLL)
On-chip PLL generates system clock timing (VCLK) by tracking the input HFLB and horizontal resolution
register (HORR). The frequency of VCLK is determined using the following equation:
VCLK Freq = HFLB Freq * HORR * 12
The VCLK frequency ranges from 5MHz to 90MHz and is selected by VCO1and VCO0. In addition,
when HFLB input is not present for MTV016, the PLL will generate a specific system clock,
approximately 2.5MHz, by a built-in oscillator to ensure data integrity.
3.6 Display & Row Control Registers
5/11
MTV016 Revision 2.0 01/01/1999
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for MTV016 electronic component. |
| Information | Total 11 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ MTV016.PDF Datasheet ] | |
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