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PDF MTV012A Data sheet ( Hoja de datos )
| Número de pieza | MTV012A | |
| Descripción | 8051 Embedded CRT Monitor Controller Mask Version | |
| Fabricantes | Myson | |
| Logotipo |  |
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1. MTV012A  Hay una vista previa y un enlace de descarga de MTV012A (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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MYSON
TECHNOLOGY
MTV012A
8051 Embedded CRT Monitor Controller
Mask Version
FEATURES
8051 core.
256 bytes internal RAM.
8K bytes program Mask ROM.
14 channels 10V open drain PWM DAC, 10 dedicated channels and 4 channels shared with I/O pin.
20 bi-direction I/O pin, 12 dedicated pin, 4 shared with DAC, 4 shared with DDC/IIC interface.
3 output pins shared with H/V sync output and self test output pins.
SYNC processor for composite sync separation, polarity and frequency check, and polarity adjustment.
Built-in monitor self test pattern generator.
Built-in Low Power Reset circuit.
IIC interface for DDC1/DDC2B and EEPROM, only one EEPROM needed to store DDC1/DDC2B and
display mode information.
Watch dog timer with programmable interval.
40 pin PDIP package.
GENERAL DESCRIPTION
The MTV012A micro controller is an 8051 CPU core-embedded device specially tailored to CRT monitor
applications. It includes an 8051 CPU core, 256-byte SRAM, 14 built-in PWM DACs, DDC1/DDC2B
interface, 24Cxx series EEPROM interface and an 8K-byte internal program ROM.
BLOCK DIAGRAM
P1.0-7
P0.0-7
RD
X1 WR
8051
X2 CORE INT1
P2.0-3
RST
P3.0-P3.2 P3.4 P2.4-7
P0.0-7
RD
WR
XFR
WATCH-DOG
TIMER
RST
STOUT
HSYNC
H/VSYNC VSYNC
CONTROL HBLANK
VBLANK
DA0-9
14 CHANNEL
PWM DAC
DA10-13
HSCL
HSDA
DDC 1/2 B & FIFO
INTERFACE
ISCL
IIC INTERFACE
ISDA
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification
without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the
product.
1/14
MTV012A Revision 1.1 12/23/1998
1 page  
MYSON
TECHNOLOGY
MTV012A
4. H/V SYNC Processing
The H/V SYNC processing block performs the functions of composite signal separation, SYNC input
presence check, frequency counting, and polarity detection and control, as well as protection of
VBLANK output while VSYNC speeds up to a high DDC communication clock rate. The present and
frequency function block treat any pulse shorter than 1 OSC period as noise.
4.1 Composite SYNC Separate
MTV012A continuously monitors the input HSYNC. If the vertical SYNC pulse can be extracted from the
input, a CVpre flag is set and the user can select the extracted "CVSYNC" for the source of polarity
check, frequency count and VBLANK. The CVSYNC will have a 10-16 us delay compared to the original
signal. The delay depends on the OSC frequency and composite mix method.
4.2 H/V Frequency Counter
MTV012A can discriminate between HSYNC/VSYNC frequency and saves the information in XFRs. The
15-bit H counter counts the time of the 64xHSYNC period, but only 11 upper bits are loaded into the
HCNTH/HCNTL latch.
The 11-bit output value will be (2/Hfreq) / (1/OSCfreq), updated once per VSYNC/CVSYNC period when
VSYNC/CVSYNC is present, or continuously updated when VSYNC/CVSYNC is not present. The 14-bit
V counter counts the time between 2 VSYNC pulses, but only 9 upper bits are loaded into the
VCNTH/VCNTL latch. The 9-bit output value will be (1/Vfreq) / (512/OSCfreq), updated every
VSYNC/CVSYNC period. An extra overflow bit indicates the condition of H/V counter overflow. The
VFchg/HFchg interrupt is active when VCNT/HCNT value changes or overflows. Tables 4.2.1 and 4.2.2
show the HCNT/VCNT value under the 8MHz OSC operations.
4.2.1 H-Freq Table
H-Freq(KHZ)
Output Value (11 bits)
8MHz OSC (hex / dec) 12MHz OSC (hex / dec)
1 30
215h / 533
320h / 800
2 31.5
1FBh / 507
2F9h / 761
3 33.5
1DDh /477
2CCh / 716
4 35.5
1C2h / 450
2A4h / 676
5 36.8
1B2h / 434
28Ch / 652
6 38
1A5h / 421
277h / 631
7 40
190h / 400
258h / 600
8 48
14Dh / 333
1F4h / 500
9 50
140h / 320
1E0h / 480
10 57
118h / 280
1A5h / 421
11 60
10Ah / 266
190h / 400
12 64
0FAh / 250
177h / 375
13 100
0A0h / 160
0F0h / 240
*1. The H-Freq output (HF10 - HF0) is valid.
*2. The tolerance deviation is + 1 LSB.
4.2.2 V-Freq Table
V-Freq(Hz)
1 56.25
2 59.94
3 60
4 60.32
Output Value (9 bits)
8MHz OSC (hex / dec) 12MHz OSC (hex / dec)
115h / 277
1A0h / 416
104h / 260
187h / 391
104h / 260
186h / 390
103h / 259
184h / 388
MTV012A Revision 1.1 12/23/1998
5/14
5 Page 
MYSON
TECHNOLOGY
MTV012A
MCTR
INTEN
FIFO
WDT
SLVCTR
SLVSTUS
SLVINT
SLVBUF
SLVADR
00h (w)
60h (w)
70h (w)
80h (w)
90h (w)
91h (r)
91h (w)
92h (r)
93h (w)
LS1
EHPR
FIFO7
WEN
ENSLV
WADR
X
SLVbuf7
SLVadr7
LS0
EVPR
FIFO6
WCLR
SLVsel
SLVS
X
SLVbuf6
SLVadr6
LDFIFO
EHPL
FIFO5
CLRDDC
ESLVBI
SLVBI
X
SLVbuf5
SLVadr5
M256
EVPL
FIFO4
DIV253
ESLVMI
SLVMI
SLVMI
SLVbuf4
SLVadr4
M128
EHF
FIFO3
LVSEL
X
X
X
SLVbuf3
SLVadr3
ACK
EVF
FIFO2
WDT2
X
X
X
SLVbuf2
SLVadr2
P
EFIFO
FIFO1
WDT1
X
X
X
SLVbuf1
SLVadr1
S
EMI
FIFO0
WDT0
X
X
X
SLVbuf0
X
MCTR (w) : Master IIC interface control register.
LS1, LS0
= 11 → FIFOL is the status which has a FIFO depth of < 5.
= 10 → FIFOL is the status which has a FIFO depth of < 4.
= 01 → FIFOL is the status which has a FIFO depth of < 3.
= 00 → FIFOL is the status which has a FIFO depth of < 2.
LDFIFO
= 1 → FIFO will be written while S/W reads MBUF.
M256
= 1 → Disables host writing EEPROM when address is over 256.
M128
= 1 → Disables host writing EEPROM when address is over 128.
ACK
= 1 → In receiving mode, there is no acknowledgment by MTV012A.
= 0 → In receiving mode, ACK is returned by MTV012A.
S, P = ↑,0 → Start condition when Master IIC is not transferring.
= X,↑ → Stop condition when Master IIC is not transferring.
= 1,X → Will resume transfer after a read/write MBUF operation.
= X,0 → Forces HSCL low and occupies the IIC bus.
* MTV012A uses a 100KHz clock to sample the S/P bit; any pulse should sustain at least 20us.
* A write/read MBUF operation can be recognized only after 10us of the MI flag's rising edge.
MSTUS (r) : Master IIC interface status register.
SCLERR
= 1 → The ISCL pin is pulled-low by other devices during the
transfer, and cleared when S=0.
DDC2
= 1 → DDC2B is active.
= 0 → MTV012A remains in DDC1 mode.
BERR
= 1 → IIC bus error, no ACK received from the slave, updated every time
when slave sends ACK on the ISDA pin.
HFREQ
= 1 → MTV012A detects a higher than 200Hz clock on the VSYNC pin.
FIFOH
= 1 → FIFO high indicated.
FIFOL
= 1 → FIFO low indicated.
BUSY
= 1 → Host drives the HSCL pin to low.
* While writing FIFO, the FIFOH/FIFOL flag will reflect the FIFO condition after 30us.
INTFLG (w) :
FIFOI
MI
Interrupt flag. An interrupt event will set its individual flag and, if the corresponding
interrupt enable bit is set, the 8051 INT1 source will be driven by a zero level. Software
MUST clear this register while serving the interrupt routine.
= 1 → No action.
= 0 → Clears FIFOI flag.
= 1 → No action.
= 0 → Clears Master IIC bus interrupt flag (MI).
INTFLG (r) : Interrupt flag.
FIFOI = 1 → Indicates the FIFO low condition; when EFIFO is set, MTV012A will be
interrupted by INT1.
MI = 1 → Indicates when a byte is sent/received to/from the IIC bus; when EEPI is
active, MTV012A will be interrupted by INT1.
INTEN (w) : Interrupt enabler.
EFIFO = 1 → Enables FIFO interrupt.
11/14
MTV012A Revision 1.1 12/23/1998
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet MTV012A.PDF ] | |
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