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PDF NT511740C5J Data sheet ( Hoja de datos )
| Número de pieza | NT511740C5J | |
| Descripción | Fast Page Mode with EDO DRAM | |
| Fabricantes | Nanya Technology | |
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NT5117405J
4,194,304-word X 4-bit
Dynamic RAM : Fast Page Mode with EDO
NT 511740C5J
Data Sheet
1 NANYA TECHNOLOGY CORP. reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORP
1 page  
NT5117405J
4,194,304-word X 4-bit
Dynamic RAM : Fast Page Mode with EDO
5. BLOCK DIAGRAM
RAS
CAS
Timing
Generator
Timing
Generator
Column
11 A d d r e s s
Buffer
11
A0-A10
Internal
Address
Counter
Refresh
Control Clock
11
Row
Address
Buffer
Row
11
Decoders
VCC
On Chip
VBB Generator
On Chip
IVCC Generator
VSS
Word
Drivers
Column
Decoders
Write
Clock
Generator
WE
OE
Sense
Amplifiers
4
I/O
Selector
Output
4 Buffers
4 4 DQ1-DQ4
Input
44
Buffers
Memory
Cells
5 NANYA TECHNOLOGY CORP. reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORP
5 Page 
NT5117405J
4,194,304-word X 4-bit
Dynamic RAM : Fast Page Mode with EDO
Notes:
1. A start-up delay of 200 µs is required after po/WEr-up,follo/WEd by a minimum of eight
initialization cycles (/RAS-only refresh or /CAS before /RAS refresh) before proper device operation
is achieved.
2. The AC characteristics assume tT=2 ns.
3. VIH(Min.) and VIL(Max.) are reference levels for measuring input timing signals. Transition time (tT)
are measured bet/WEen VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only . If tRCD is greater than the specified
tRCD (Max.) limit, access time is controlled by tCAC.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only . If tRAD is greater than the specified
tRAD (Max.) limit, access time is controlled by tAA.
7. tCEZ (Max.), tREZ (Max.), t/WEZ (Max.) and t/OEZ (Max.) define the time at which the output achieves the
open circuit condition and are not referenced to output voltage levels.
8. tCEZ and tREZ must be satisfied for open circuit condition .
9. tRCH or tRRH must be satisfied for a read cycle.
10. tWCS, tCWD, tRWD, tAWD, and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only . If tWCS¡ÙtWCS(Min.), the cycle is an early write cycle and the
data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD¡ÙtCWD(Min.) ,
tRWD¡ÙtRWD(Min.) , tAWD¡ÙtAWD(Min.) and tCPWD¡ÙtCPWD(Min.), the cycle is a read modify write cycle
and data out will contain data read from the selected cell; if neither of the above sets of conditions is
satisfied, the condition of the data out (at access time) is indeterminate.
11. These parameters are referenced to /CAS leading edge in an early write cycle, and to /WE leading
edge in an /OE control write cycle or a read modify write cycle .
12. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. In a test mode CA0 and CA1 are not
used and each DQ pin now accesses 8-bit locations .Since all 4 DQ pins are used, a total of 32
data bits can be written in parallel into the memory array. In a read cycle, if 8 data bits are equal the
DQ pin will indicate a high level. If the 8 data bits are not equal, the DQ pin will indicate a low level.
The test mode is cleared and the memory device returned to its normal operating state by performing
a /RAS-only refresh cycle or a /CAS before /RAS refresh cycle.
13. In a test mode read cycle , the value of access time parameters is delayed for 5 ns for the specified
value . These parameters should be specified in test mode cycle by adding the above value to the
specified value in this data sheet.
11
NANYA TECHNOLOGY CORP. reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORP
11 Page | ||
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| PDF Descargar | [ Datasheet NT511740C5J.PDF ] | |
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