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PDF SY100EL15L Data sheet ( Hoja de datos )
| Número de pieza | SY100EL15L | |
| Descripción | 3.3V 1:4 CLOCK DISTRIBUTION | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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Micrel
Synergy™ High-Speed Products
3.3V 1:4 CLOCK
DISTRIBUTION
ClockWorks™
ClockWSYo1r0k0sE™L15L
SY100EL15L
FEATURES
s 3.3V power supply
s 50ps output-to-output skew
s Low power
s Synchronous enable/disable
s Multiplexed clock input
s 75KΩ internal input pull-down resistors
s ESD protection of 2000V
s Available in 16-pin SOIC package
PIN CONFIGURATION/BLOCK DIAGRAM
VCC EN SCLK CLK CLK VBB SEL VEE
16 15 14 13 12 11 10 9
10
D
Q
12 3 456 7 8
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
SOIC
TOP VIEW
DESCRIPTION
The SY100EL15L is a low skew 1:4 clock distribution
IC designed explicitly for low skew clock distribution
applications. The device can be driven by either a
differential or single-ended ECL or, if positive power
supplies are used, PECL input signal. If a single-ended
input is to be used the VBB output should be connected
to the CLK input and bypassed to ground via a 0.01µF
capacitor. The VBB output is designed to act as the
switching reference for the input of the EL15 under single-
ended input conditions. As a result, this pin can only
source/sink up to 0.5mA of current.
The EL15 features a multiplexed clock input to allow
for the distribution of a lower speed scan or test clock
along with the high speed system clock. When LOW (or
left open and pulled LOW by the input pull-down resistor)
the SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the
outputs will only be enabled/disabled when they are
already in the LOW state. This avoids any chance of
generating a runt clock pulse when the device is enabled/
disabled as can happen with an asynchronous control.
The internal flip flop is clocked on the falling edge of the
input clock, therefore all associated specification limits
are referenced to the negative edge of the clock input.
When both differential inputs are left open, CLK input
will pull down to VEE and CLK input will bias around
VCC/2.
PIN NAMES
Pin
CLK
SCLK
EN
SEL
VBB
Q0-3
Function
Differential Clock Inputs
Synchronous Clock Input
Synchronous Enable
Clock Select Input
Reference Output
Differential Clock Outputs
TRUTH TABLE
CLK
SCLK
SEL
L XL
H XL
X LH
X HH
X XX
* On next negative transition of CLK or SCLK
EN
L
L
L
L
H
Q
L
H
L
H
L*
© 1999 Micrel
Rev.: A
Amendment: /0
1 Issue Date: December 1999
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet SY100EL15L.PDF ] | |
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