PDF SY100E016 Data sheet ( Hoja de datos )

Número de pieza	SY100E016
Descripción	8-BIT SYNCHRONOUS BINARY UP COUNTER
Fabricantes	Micrel Semiconductor
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No Preview Available ! 8-BIT SYNCHRONOUS BINARY UP COUNTER SY10E016 SY100E016 FINAL FEATURES s 700MHz min. count frequency s Extended 100E VEE range of –4.2V to –5.5V s 1000ps CLK to Q, TC s Internal, gated TC feedback s 8 bits wide s Fully synchronous counting and TC generation s Asynchronous Master Reset s Fully compatible with industry standard 10KH, 100K I/O levels s Internal 75KΩ input pulldown resistors s Fully compatible with Motorola MC10E/100E016 s Available in 28-pin PLCC package DESCRIPTION The SY10/100E016 are high-speed synchronous, presettable and cascadable 8-bit binary counters designed for use in new, high-performance ECL systems. Architecture and operation are the same as the Motorola MC10H016 in the MECL 10KH family, extended to 8 bits, as shown in the logic diagram. The counters feature internal feedback of TC, gated by the TCLD (terminal count load) pin. When TCLD is LOW, the TC feedback is disabled and counting proceeds continuously, with TC going LOW to indicate an all-HlGH state. When TCLD is HIGH, the TC feedback causes the counter to automatically reload upon TC = LOW, thus functioning as a programmable counter. PIN CONFIGURATION MR CLK TCLD VEE NC P0 P1 25 24 23 22 21 20 19 26 18 27 17 28 PLCC 16 1 TOP VIEW 15 2 J28-1 14 3 13 4 12 5 6 7 8 9 10 11 Q7 Q6 VCC Q5 VCCO Q4 Q3 PIN NAMES Pin P0-P7 Q0-Q7 CE PE MR CLK TC TCLD VCCO Function Parallel Data (Preset) Inputs Data outputs Count Enable Control Input Parallel Load Enable Control Input Master Reset Clock Terminal Count Output TC-Load Control Input VCC to Output Rev.: D Amendment: /2 1 Issue Date: May, 1998 1 page Micrel SY10E016 SY100E016 APPLICATIONS INFORMATION Cascading Multiple E016 Devices For applications which call for larger than 8-bit counters, multiple E016s can be tied together to achieve very wide bit width counters. The active low terminal count (TC) output and count enable input (CE) greatly facilitate the cascading of E016 devices. Two E016s can be cascaded without the need for external gating; however, for counters wider than 16 bits, external OR gates are necessary for cascade implementations. Figure 1, below, pictorially illustrates the cascading of 4 E016s to build a 32-bit high frequency counter. Note the E101 gates used to OR the terminal count outputs of the lower order E016s to control the counting operation of the higher order bits. When the terminal count of the preceding device (or devices) goes low (the counter reaches an all 1s state), the more significant E016 is set in its count mode and will count one binary digit upon the next positive clock transition. In addition, the preceding devices will also count one bit, thus sending their terminal count outputs back to a high state, disabling the count operation of the more significant counters and placing them back into hold modes. Therefore, for an E016 in the chain to count all of the lower order terminal count outputs, it must be in the low state. The bit width of the counter can be increased or decreased by simply adding or subtracting E016 devices from Figure 1 and maintaining the logic pattern illustrated in the same figure. The maximum frequency of operation for the cascaded counter chain is set by the propagation delay of the TC output and the necessary set-up time of the CE input and the propagation delay through the OR gate controlling it (for 16- bit counters the limitation is only the TC propagation delay and the CE set-up time). Figure 1 shows E101 gates used to control the count enable inputs; however, if the frequency of operation is lower, a slower ECL OR gate can be used. Using the worst case guarantees for these parameters from the ECLinPS data book, the maximum count frequency for a greater than 16-bit counter is 475MHz and that for a 16-bit counter is 625MHz. Note that this assumes the trace delay between the TC outputs and the CE inputs are negligible. If this is not the case, estimates of these delays need to be added to the calculations. LOAD "LO" Q0–Q7 CE PE Q0–Q7 CE PE Q0–Q7 CE PE Q0–Q7 CE PE E016 LSB E016 E016 E016 MSB CLK TC P0–P7 CLK TC P0–P7 E101 CLK TC P0–P7 E101 CLK TC P0–P7 CLOCK Figure 1. 32-Bit Cascaded E016 Counter 5 5 Page

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