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PDF SY100E193 Data sheet ( Hoja de datos )
| Número de pieza | SY100E193 | |
| Descripción | ERROR DETECTION/ CORRECTION CIRCUIT | |
| Fabricantes | Micrel Semiconductor | |
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ERROR DETECTION/
CORRECTION CIRCUIT
SY10E193
SY100E193
FEATURES
s Hamming code generation
s Extended 100E VEE range of –4.2V to –5.5V
s 8-bit wide
s Expandable for more width
s Provides parity register
s Fully compatible with industry standard 10KH,
100K ECL levels
s Internal75KΩ input pulldown resistors
s Fully compatible with Motorola MC10E/100E193
s Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E193 are error detection and correction
(EDAC) circuits designed for use in new, high- performance
ECL systems. The E193 generates hamming parity codes
on an 8-bit word as shown in the block diagram. The P5
output gives the parity of the whole word. PGEN provides
word parity after Odd/Even parity control and gating with
the BPAR input. PGEN also feeds into a 1-bit shiftable
register for use as part of a scan ring.
The combinatorial part of the device generates the same
code pattern as the Motorola MC10193.
Used in conjunction with 12-bit parity generators, such
as the E160, a SECDED (single error correction, double
error detection) error system can be designed for a multiple
of an 8-bit word.
PIN CONFIGURATION
EV/OD
BPAR
B0
VEE
B1
B2
B3
25 24 23 22 21 20 19
26 18
27 17
28 TOP VIEW 16
1 PLCC 15
2
J28-1
14
3 13
4 12
5 6 7 8 9 10 11
PARERR
PARERR
VCC
P5
VCCO
P4
P3
PIN NAMES
Pin
B0–B7
BPAR
EV/OD
EN
HOLD
S-IN
SHIFT
CLK
P1–P5
PGEN
PARERR/PARERR
VCCO
Function
Check Bit Inputs
Check Bit Parity Input
Even/Odd Parity Select
Parity Enable
Syndrome Hold Input
Syndrome Bit Input
Syndrome Bit Shift
Clock Input
Parity Output
Parity Generate Output
Parity Error Output
VCC to Output
Rev.: C
Amendment: /1
1 Issue Date: February, 1998
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet SY100E193.PDF ] | |
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