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PDF SY100E171 Data sheet ( Hoja de datos )
| Número de pieza | SY100E171 | |
| Descripción | 3-BIT 4:1 MULTIPLEXER | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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3-BIT 4:1
MULTIPLEXER
SY10E171
SY100E171
FEATURES
s 725ps max. D to output
s Extended 100E VEE range of –4.2V to –5.5V
s Differential outputs
s Split select architecture
s Fully compatible with industry standard 10KH,
100K ECL levels
s Internal 75KΩ input pulldown resistors
s Fully compatible with Motorola MC10E/100E171
s Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E171 offer three 4:1 multiplexers with
differential outputs, designed for use in new, high-
performance ECL systems. The leading 4-bit multiplexer
operation is organized pairwise, with each pair being a 2-
bit multiplexer. Separate select (SEL1A, SEL1B) controls
are provided within each pair. The SEL1A and SEL1B
signals control the leading multiplexers, while the SEL2
signal controls the output multiplexer. The three select
signals can be used to determine which of the four data
inputs will be propagated to the corresponding outputs.
BLOCK DIAGRAM
D0a
D0b
D0c
D0d
D1a
D1b
D1c
D1d
D2a
D2b
D2c
D2d
SEL1A
SEL1B
SEL2
2:1
MUX
SEL
2:1
MUX
SEL
2:1
MUX
SEL
2:1
MUX
SEL
2:1
MUX
SEL
2:1
MUX
SEL
PIN CONFIGURATION
2:1
MUX
SEL
Q0
Q0
2:1
MUX
SEL
Q1
Q1
SEL1A
SEL1B
SEL2
VEE
NC
NC
D1c
25 24 23 22 21 20 19
26 18
27 17
28 16
1
TOP VIEW
15
PLCC
2
J28-1
14
3 13
4 12
5 6 7 8 9 10 11
Q2
Q2
VCC
Q1
Q1
VCCO
Q0
2:1 Q2 PIN NAMES
MUX
SEL Q2
Pin
D0x–D2x
SEL1A, SEL1B
SEL2
Q0–Q2
Q0–Q2
VCCO
Function
Data Inputs
First-stage Select Inputs
Second-stage Select Input
True Output
Inverted Output
VCC to Output
Rev.: C
Amendment: /1
1 Issue Date: February, 1998
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet SY100E171.PDF ] | |
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