DataSheetWiki


SY100E137 fiches techniques PDF

Micrel Semiconductor - 8-BIT RIPPLE COUNTER

Numéro de référence SY100E137
Description 8-BIT RIPPLE COUNTER
Fabricant Micrel Semiconductor 
Logo Micrel Semiconductor 





1 Page

No Preview Available !





SY100E137 fiche technique
8-BIT RIPPLE
COUNTER
SY10E137
SY100E137
FEATURES
s 1.8GHz min. count frequency
s Extended 100E VEE range of –4.2V to –5.5V
s Synchronous and asynchronous enable pins
s Differential clock input and data output pins
s VBB output for single-ended use
s Asynchronous Master Reset
s Internal 75Kinput pull-down resistors
s Available in 28-pin PLCC packge
PIN CONFIGURATION
A_Start
EN1
EN2
VEE
CLK
CLK
VBB
25 24 23 22 21 20 19
26 18
27 17
28
PLCC
16
1
TOP VIEW
15
2
J28-1
14
3 13
4 12
5 6 7 8 9 10 11
Q4
Q4
VCC
Q3
Q3
Q2
Q2
PIN NAMES
Pin
CLK, CLK
Q0–Q7, Q0–Q7
A_Start
EN1, EN2
MR
VBB
VCCO
Function
Differential Clock Inputs
Differential Q Outputs
Asynchronous Enable Input
Synchronous Enable Inputs
Asynchronous Master Reset
Switching Reference Output
VCC to Output
DESCRIPTION
The SY10/100E137 are very high speed binary ripple
counters. The two least significant bits were designed
with very fast edge rates, while the more significant bits
maintain standard ECLinPS output edge rates. This allows
the counters to operate at very high frequencies, while
maintaining a moderate power dissipation level.
The devices are ideally suited for multiple frequency
clock generation, as well as for counters in high-
performance ATE time measurement boards.
Both asynchronous and synchronous enables are
available to maximize the device's flexibility for various
applications. The asynchronous enable input, A_Start,
when asserted, enables the counter while overriding any
synchronous enable signals. The E137 features XOR'ed
enable inputs, EN1 and EN2, which are synchronous to
the CLK input. When only one synchronous enable is
asserted, the counter becomes disabled on the next CLK
transition. All outputs remain in the previous state poised
for the other synchronous enable or A_Start to be
asserted in order to re-enable the counter. Asserting
both synchronous enables causes the counter to become
enabled on the next transition of the CLK. EN1 (or EN2)
and CLK edges are coincident. Sufficient delay has been
inserted in the CLK path (to compensate for the XOR
gate delay and the internal D-flip-flop set-up time) to
ensure that the synchronous enable signal is clocked
correctly; hence, the counter is disabled.
The E137 can also be driven single-endedly utilizing
the VBB output supply as the voltage reference for the
CLK input signal. If a single-ended signal is to be used,
the VBB pin should be connected to the CLK input and
bypassed to ground via a 0.01µF capacitor. VBB can
only source/sink 0.5mA; therefore, it should be used as
a switching reference for the E137 only.
All input pins left open will be pulled LOW via an input
pull-down resistor. Therefore, do not leave the differential
CLK inputs open. Doing so causes the current source
transistor of the input clock gate to become saturated,
thus upsetting the internal bias regulators and
jeopardizing the stability of the device.
The asynchronous Master Reset resets the counter to
an all zero state upon assertion.
Rev.: C Amendment: /1
1 Issue Date: February, 1998

PagesPages 4
Télécharger [ SY100E137 ]


Fiche technique recommandé

No Description détaillée Fabricant
SY100E131 4-BIT D FLIP-FLOP Micrel Semiconductor
Micrel Semiconductor
SY100E136 6-BIT UNIVERSAL UP/DOWN COUNTER Micrel Semiconductor
Micrel Semiconductor
SY100E137 8-BIT RIPPLE COUNTER Micrel Semiconductor
Micrel Semiconductor

US18650VTC5A

Lithium-Ion Battery

Sony
Sony
TSPC106

PCI Bus Bridge Memory Controller

ATMEL
ATMEL
TP9380

NPN SILICON RF POWER TRANSISTOR

Advanced Semiconductor
Advanced Semiconductor


www.DataSheetWiki.com    |   2020   |   Contactez-nous  |   Recherche