EP1S80B956 Datasheet PDF - Altera
| Part Number | EP1S80B956 | |
| Description | (EP1S10 - EP1S80) Stratix Device | |
| Manufacturers | Altera | |
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There is a preview and EP1S80B956 download ( pdf file ) link at the bottom of this page. Total 30 Pages | ||
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Section I. Stratix Device
Family Data Sheet
This section provides designers with the data sheet specifications for
Stratix devices. They contain feature definitions of the internal
architecture, configuration and JTAG boundary-scan testing information,
DC operating conditions, AC timing parameters, a reference to power
consumption, and ordering information for Stratix devices.
This section contains the following chapters:
■ Chapter 1. Introduction
■ Chapter 2. Stratix Architecture
■ Chapter 3. Configuration & Testing
■ Chapter 4. DC & Switching Characteristics
■ Chapter 5. Reference & Ordering Information
Revision History The table below shows the revision history for Chapter 1 through
Chapter 5.
Chapter
Date/Version
Changes Made
1 September 2004, v3.1 ● Updated Table 1–6 on page 1–5.
April 2004, v3.0 ● Main section page numbers changed on first page.
● Changed PCI-X to PCI-X 1.0 in “Features” on page 1–2.
● Global change from SignalTap to SignalTap II.
mJanuary 2004, v2.2
.coOctober 2003, v2.1
uJuly 2003, v2.0
● The DSP blocks in “Features” on page 1–2 provide dedicated
implementation of multipliers that are now “faster than 300 MHz.”
● Updated -5 speed grade device information in Table 1-6.
● Add -8 speed grade device information.
● Format changes throughout chapter.
www.datasheet4Altera Corporation
Section I–1
Preliminary
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Stratix Device Family Data Sheet
Chapter
4
Date/Version
Changes Made
● Updated Table 4–123 on page 4–87 through Table 4–126 on
page 4–94.
● Updated Note 3 in Table 4–123 on page 4–87.
● Table 4–125 on page 4–90: moved to correct order in chapter, and
updated table.
● Updated Table 4–126 on page 4–94.
● Updated Table 4–127 on page 4–96.
● Updated Table 4–128 on page 4–97.
April 2004, v3.0
● Table 4–129 on page 4–98: updated table and added Note 10.
● Updated Table 4–130 and Table 4–131 on page 4–100.
● Updated Table 4–110 on page 4–75.
● Updated Table 4–123 on page 4–87.
● Updated Table 4–124 on page 4–89. through Table 4–126 on
page 4–94.
● Added Note 10 to Table 4–129 on page 4–98.
● Moved Table 4–127 on page 4–96 to correct order in the chapter.
● Updated Table 4–130 on page 4–100 through Table 4–131 on
page 4–100.
● Deleted tXZ and tZX from Figure 4–4.
● Waveform was added to Figure 4–6.
● The vin and maximum duty cycle values in Note 3 of Table 4–8 were
moved to a new Table 4–9.
● Changes were made to values in SSTL-3 class I and II rows in
Table 4–17.
● Note 1 was added to Table 4–34.
● Added tSU_R and tSU_C rows in Table 4–38.
● Changed Table 4–55 title from “EP1S10 Column Pin Fast Regional
Clock External I/O Timing Parameters” to “EP1S10 External I/O
Timing on Column Pins Using Fast Regional Clock Networks.”
● Changed values in Tables 4–46, 4–48 to 4–51, 4–128, and 4–130.
● Added tARESET row in Tables 4–127 to 4–131.
● Deleted -5 Speed Grade column in Tables 4–117 to 4–119 and 4–122
to 4–123.
● Fixed differential waveform in Figure 4–1.
● Added “Definition of I/O Skew” section.
● Added tSU and tCO_C rows and made changes to values in tPRE and
tCLKHL rows in Table 4–46.
● Values changed in the tSU and tH rows in Table 4–47.
● Values changed in the tM4KCLKHL row in Table 4–49.
● Values changed in the tMRAMCLKHL row in Table 4–50.
● Added Table 4–51 to “Internal Timing Parameters” section.
● The timing information is preliminary in Tables 4–55 through 4–96.
● Table 4–111 was separated into 3 tables: Tables 4–111 to 4–113.
November 2003, v2.2 ● Updated Tables 4–127 through 4–129.
Altera Corporation
1–5
Preliminary
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for EP1S80B956 electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ EP1S80B956.PDF Datasheet ] | |
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