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ZR36015 fiches techniques PDF

ZORAN - RASTER TO BLOCK CONVERTER

Numéro de référence ZR36015
Description RASTER TO BLOCK CONVERTER
Fabricant ZORAN 
Logo ZORAN 





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ZR36015 fiche technique
PRELIMINARY
FEATURES
s Real Time Raster to/from Block Conversion
s 1/2 Decimation Processing in the Horizontal Direction
s 30 MHz Maximum Clock Rate
s Only Image in Preset Window is Converted
s Compatable with Zorans ZR36050 JPEG Coder and
ZR36011 Color Space Converter
ZR36015
RASTER TO BLOCK CONVERTER
s Supports 1:0:0,4:2:2,and 4:1:1 data formats
s 100-pin plastic quad flat package (PQFP)
s TTL level Input/Output
s Synchronous data and controls
s Low power consumption: 0.45W (Typ.)
s CMOS circuit operating with a single 5V power supply
APPLICATIONS
s Image processing
s Multi-media
s Scanners
s Image Storage
s Image Capture
DESCRIPTION
The ZR36015 performes raster to/from block conversion for
image compression and expansion applications, and it can be
connected directly to the ZR36050 JPEG coder and the
ZR36011 Color Space Converter.
An image compression system can be easily constructed using
the ZR36015 with the ZR35060 and ZR36011.
The ZR36015 uses a double buffered external SRAM Strip
Buffer to support raster to/from block conversion and block inter-
leave.
The maximum number of pixels that can be processed per line
is 8K. The maximum number of lines that can be prcessed per
image is 16K. These numbers vary according to the mode of
operation.
The ZR36015 supports 4:0:0, 4:1:1, and 4:2:2 data formats, and
one half decimation in horizontal direction during compression.
The maximum data transfer rate to the ZR36050 coder is 30
MHz.
[The ZR36015 is fabricated with an advanced low-power CMOS
technology, making it suitable for use in low-power, cost sensi-
tive applications. The device is availiable in a 100 pin , Plastic
Quad Flat Package (PQFP).]
Host Interface
SPH WR
RD ADD(1:0)
CBSY
PXDATA(15:0)
Pixel
Interface
HEN
VEN
WINDOW
BSY
CLKCSC
Internal Register Control
Raster/Block
Address
Generator
1/2
Decimation
Window
Control
Interface Logic
I/F
DSYNC
EOS
STOP
COE
BDATA(7:0)
Coder Interface
MWE
MOE
MADD(15:0)
Memory
Interface
MDATA(15:0)
RESET
SYSCLK
Pixel
Interface
8
PXDATA(15:0)
MWE
CBUSY
HEN
VEN
WINDOW
BSY
MOE
MADD(15:0)
16
16
MDATA(15:0)
CLKCSC
Host
Interface
System
Clock
System
Reset
SPH
RD
WR
2 ADD(1:0)
SYSCLK
RESET
8
BDATA(7:0)
COE
EOS
STOP
DSYNC
Memory
Interface
Coder
Interface
Figure 1. ZR36015 Block Diagram
Figure 2. ZR36015 Logical Pinout
ZORAN Corporation s 1705 Wyatt Drive s Santa Clara, CA 95054 s (408) 986-1314 s FAX (408) 986-1240
June 1993
This document was created with FrameMaker 4.0.4

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