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PDF MTV512M Data sheet ( Hoja de datos )
| Número de pieza | MTV512M | |
| Descripción | 8051 Embedded Monitor Controller 64K Falsh Type | |
| Fabricantes | Myson Century | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MTV512M (archivo pdf) en la parte inferior de esta página. Total 26 Páginas | ||
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MTV512M
Preliminary
8051 Embedded Monitor Controller 64K Flash Type
GENERAL DESCRIPTIONS
The MTV512M micro-controller is an 8051 CPU core
embedded device especially tailored for flat panel
display applications. It includes an 8051 CPU core,
768-byte SRAM, 4 channels of 6-bit ADC, 3 external
counters/timers, 6 channels of PWM DAC, VESA
DDC interface, and a 64K-byte internal program
Flash-ROM memory in 44-pin PLCC package.
FEATURES
• 8051 core, 12MHz operating frequency with
single/double CPU clock option
• 0.35um process; 3.3V power supply
• 768-byte RAM; 64K-byte program Flash memory
• Maximum 6 channels of PWM DAC
• Compliant with VESA DDC1/2B/2Bi/2B+ standard
• Dual slave IIC addresses; two H/W auto transfer
DDC1/DDC2x data for both D-sub and DVI
interfaces
• Watchdog timer with programmable interval
• Support external counters/timers, 1 & 2
• Single/double frequency clock output
• Two external interrupts, INT1 is shared with Slave
IIC interrupt source.
• Maximum 4 channels of 6-bit ADC
• Flash-ROM code protection selection
• 44-pin PLCC package
BLOCK DIAGRAM
P1.0-7
P3.0-2
P3.4
8051
CORE
RST
X1
X2
CKO
P0.0-7
P2.0-3
RD
WR
ALE
INT1
P0.0-7
P2.0-7
RD
WR
ALE
INT1
XFR
ADC
AD0-3
AUXRAM &
DDCRAM1 &
DDCRAM2
PWM DAC
P7.6-7
DA0-5
P6.0-7
P5.0-6
AUX
I/O
DDC & IIC HSCL1
INTERFACE HSDA1
HSCL2
HSDA2
t4u.com*This datasheet, which contains proprietary and trade secret information of MYSON CENTURY, INC., is
confidential and subject to various privileges against unauthorized disclosure.
tasheeMyson Century, Inc.
aNo. 2, Industry East Rd. III,
.dScience-Based Industrial Park, Hsin-Chu, Taiwan
wwwTel: 886-3-5784866 Fax: 886-3-5784349
www.myson.com.tw
Rev. 0.4 August 25, 2003
page 1 of 1
1 page  
Name
VSYNC
Pin No. Direction
Default
Direction
32 I
I
Default
Output
Value
0
MTV512M
Preliminary
Internal
Pull
Up/Down
down
Pin Type
Description
Input VSYNC input
NC 33 - - - - - No connection
NC 34 - - - - - No connection
NC 35 - - - - - No connection
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0/ET2
VCC
36 I/O
37 I/O
38 I/O
39 I/O
40 I/O
41 I/O
42 I/O
43 I/O
44 -
I Z - Standard General purpose I/O
8051 or (Standard 8051/CMOS)
CMOS
I Z - Standard General purpose I/O
8051 or (Standard 8051/CMOS)
CMOS
I Z - Standard General purpose I/O
8051 or (Standard 8051/CMOS)
CMOS
I Z - Standard General purpose I/O
8051 or (Standard 8051/CMOS)
CMOS
I Z - Standard General purpose I/O
8051 or (Standard 8051/CMOS)
CMOS
I Z - Standard General purpose I/O
8051 or (Standard 8051/CMOS)
CMOS
I Z - Standard General purpose I/O
8051 or (Standard 8051/CMOS)
CMOS
I Z(P1.0) - Standard General purpose I/O/External
8051 or Counter/Timer2 (Standard
CMOS 8051/CMOS)
- - - - 3.3V power
page 5 of 5
5 Page 
PORT5
PORT5
PORT5
PORT5
PORT6
PORT6
PORT6
PORT6
PORT6
PORT6
PORT6
PORT6
PORT7
PORT7
F34h(r/w)
F35h(r/w)
F36h(r/w)
F37h(r/w)
F38h(r/w)
F39h(r/w)
F3Ah(r/w)
F3Bh(r/w)
F3Ch(r/w)
F3Dh(r/w)
F3Eh(r/w)
F3Fh(r/w)
F76h(r/w)
F77h(r/w)
PORT5 (r/w) : Port 5 data input/output value.
PORT6 (r/w) : Port 6 data input/output value.
MTV512M
Preliminary
P54
P55
P56
P57
P60
P61
P62
P63
P64
P65
P66
P67
P76
P77
PWM DAC
Each output pulse width of PWM DAC converter is controlled by an 8-bit register in XFR. The frequency of
PWM clock is 47KHz or 94KHz, selected by PWMF. And the total duty cycle step of these DAC outputs is 253
or 256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to DAC register generates stable high output.
If DIV253=0, the output pulses low at least once even if the DAC register's content is FFH. Writing 00H to DAC
register generates stable low output.
Reg name
addr
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DA0 F20h(r/w)
Pulse width of PWM DAC 0
DA1 F21h(r/w)
Pulse width of PWM DAC 1
DA2 F22h(r/w)
Pulse width of PWM DAC 2
DA3 F23h(r/w)
Pulse width of PWM DAC 3
DA4 F24h(r/w)
Pulse width of PWM DAC 4
DA5 F25h(r/w)
Pulse width of PWM DAC 5
DA0-5 (r/w) : The output pulse width control for DA0-5.
* All of PWM DAC converters are centered with value 80h after power on.
DDC & IIC Interface
i) DDC1/DDC2x Mode, DDCRAM1/DDCRAM2 and SlaveA1/SlaveA2 Block
The MTV512M supports VESA DDC for both D-sub and DVI interfaces through HSCL1/HSDA1 and
HSCL2/HSDA2 pins. The HSCL1/HSDA1 pins access DDCRAM1 by SlaveA1, and the HSCL2/HSDA2 pins
access DDCRAM2 by SlaveA2. The MTV512M enters DDC1 mode for both DDC channels after Reset. In this
mode, VSYNC is used as data clock. The HSCL1/HSCL2 pin should remain at high. The data output to the
HSDA1/HSDA2 pin is taken from a shift register in MTV512M. The shift register automatically fetches EDID
page 11 of 11
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet MTV512M.PDF ] | |
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