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PDF MV20556 Data sheet ( Hoja de datos )
| Número de pieza | MV20556 | |
| Descripción | 8 - Bit MCU Mouse Controller | |
| Fabricantes | Mosel Vitelic | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MV20556 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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MOSEL VITELIC INC.
July 1997
Preliminary
Features
General 8051 instruction family compatible
Operate at voltage 5.0V.
No External Memory is supported
8 bit bus I/O ports
4 K byte ROM
128 byte RAM
128 byte depth stack
Two 16 bit Timers (Event Counters)
15 programmable I/O pins
Five interrupt sources
Programmable serial UART channel
Direct LED drive output
MV20556
8 - Bit MCU Mouse Controller
Bit operation instructions
Page free jumps
8 - bit Unsigned Division
8 - bit Unsigned Multiply
BCD arithmatic
Direct Addressing
Indirect Addressing
Nested Interrupt
Two priority level interrupt
A full duplex serial I/O port
Working at 16/25/40 MHz Clock
Full static operation: 3 MHz through 16 MHz
Description
The MVI MV20556 is an 8 - bit single chip
microcontroller. It provides hardware features and
powerful instruction set that are necessary to make it a
versatile and cost effective controller for mouse
applications which needs up to 4K byte internal
memory either for program or for data and mixed.
A serial input / output port is provided for I/O
expansion, Inter - processor communications, full
duplex UART.
Ordering Information
MV20556ajk - pqrs
a: process identifier. { C:=COMS }
jk: working clock in MHz. { 16 }
pqr: production code { 001, ..., 999 }
s: package type. { P: 20L 300 mil PDIP }
Postfix
blank
N
S
Package
dice
20L PDIP
20L SOP
Pin/Pad
Configuration
page 25
page 1
page 1
Dimension
page 25
page 23
page 24
Logo Size at
Top Marking
-
4.5 x 3.8 mm
4.0 x 3.4 mm
Pin Configuration
RES 1
RXD/P 3.0 2
TXD/P 3.1 3
XTA2 4
XTAL1 5
#INT0/P 3.2 6
#INT1/P 3.3 7
T0/P 3.4 8
T1/P 3.5 9
VSS 10
MV20556
20L PDIP
300 mil
(Top View)
20L SOP
(Top View)
20 VDD
19 P 1.7
18 P 1.6
17 P 1.5
16 P 1.4
15 P 1.3
14 P 1.2
13 P 1.1
12 P 1.0
11 P 3.7
Specifications subject to change without notice, contact your sales representatives for the most recent information.
1/27
PID256** 07/97
1 page  
MOSEL VITELIC INC.
Preliminary
MV20556
Memory Map Overall
The CPU of MV20556 is able to access three memory areas. They are:
(1) 128 bytes data RAM addressed at 00H through 7FH;
(2) 20 SFRs addressed at 80H through FFH;
(3) 4,096 bytes program ROM addressed at 000H through FFFH.
Be noted, MCU MV20556 builds all accessible memory inside, it is unable to access external memory.
4095
FFFH
255
128
127
0
Internal
Data
RAM
FFH 255
80H 128
7FH
00H
Special
Function
Register
FFH
F0H
0
Internal Program ROM
000H
Internal Memory Map
Specifications subject to change without notice, contact your sales representatives for the most recent information.
5/27
PID256** 07/97
5 Page 
MOSEL VITELIC INC.
Preliminary
MV20556
Interrupt System(Cont'd)
The highest-priority interrupt request gets serviced at
the end of the instruction-in progress unless the
request is made in the last fourteen oscillator periods of
the instruction-in-progress. Under this circumstance,
the next instruction will also execute before the
interrupt's subroutine call is made. The first instruction
of the service program will begin execution twenty-four
oscillator periods (the time required for the hardware
subroutine call) after the completion of the
instruction-in-progress or, under the circumstances
mentioned earlier, twenty-four oscillator periods after
the next instruction.
Thus, the greatest delay in response to an interrupt
request is 86 oscillator periods (approximately 7µsec @
12 MHz). Examples of the best and worst case
conditions are illustrated in right side table.
External Interrupts
The external interrupt request inputs (#INT0 and
#INT1) can be programmed for either transition-
activated or level-activated operation. Control of the
external interrupts is provided by the four low-order bits
of TCON. When IT0 and IT1 are set to one (1),
interrupt requests on #INT0 and #INT1 are
transition-activated (high-to-low); or else they are
low-level activated. IE0 and IE1 are the interrupt
request flags. These flags are set when their
corresponding interrupt request inputs at #INT0 and
#INT1, respectively, are low when sampled by the
MV20556 and the transition activated scheme is
selected by IT0 and IT1. When IT0 and IT1 are
programmed for level-activated interrupts, the IE0 and
IE1 flags are not affected by the inputs #INT0 and
INT1, respectively.
Transition-Activated Interrupts
The external interrupt request inputs (#INT0 and
#INT1) can be programmed for high-to-low
transition-activated operation. For transition-activated
operation, the input must remain low for greater than
twelve oscillator periods, but need not be synchronous
with the oscillator. It is internally latched by the
MV20556 near the falling-edge of ALE during an
instruction's tenth, twenty-second, thirty-fourth and
forty-sixth oscillator periods and, if the input is low, IE0
or IE1 is set.
The upward transition of a transition- activated input
may occur at any time after the twelve oscillator period
latching time, but the input must remain high for twelve
oscillator periods before reactivation.
Level-Activated Interrupt
The external interrupt request inputs (#INT0 and
#INT1)can be programmed for level-activated
operation. The input is sampled by the MV20556 near
the falling-edge of internal signal ALE during the
instruction's tenth (10th), twenty-second (22nd), thirty-
fourteen (34th) and forty-sixth (46th) oscillator periods.
MSB
EA
-
LSB
- ES ET1 EX1 ET0 EX0
EA IE.7 Disable all interrupts. If EA=0, no interrupt will be acknowledged. If EA=1, each interrupt source is
individually enabled or disabled by setting or clearing its enable bit. Cleared by software to disable all
interrupts, independent of the state of IE. 4-IE.0
- IE.6 Reserve for future use.
- IE.5 Reserve for future use.
ES IE.4 Enable Serial port control bit. Set/cleared by software to enable/disable interrupts from TI or RI flags.
ET1 IE.3 Enable or disable the timer 1 overflow interrupt. Set/cleared by software to enable/disable interrupts
from timer/counter 1
EX0 IE.2 Reserve for future use. Enable External interrupt 1 control bit. Set/cleared by software to
enable/disable interrupts from INT1.
ET0 IE.1 Enable or disable the timer 0 overflow interrupt. Set/cleared by software to enable/disable interrupts
from timer/counter 0
EX1 IE.0 Enable External interrupt 0 control bit. Set/cleared by software to enable/disable interrupts from INT0
IE definition
Specifications subject to change without notice, contact your sales representatives for the most recent information.
11/27
PID256** 07/97
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MV20556.PDF ] | |
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