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PDF IW4029B Data sheet ( Hoja de datos )
| Número de pieza | IW4029B | |
| Descripción | Binary or BCD-Decade Counter | |
| Fabricantes | IK Semiconductor | |
| Logotipo |  |
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TECHNICAL DATA
Presettable Up/Down Counter
High-Voltage Silicon-Gate CMOS
IW4029B
The IW4029B consists of a four-stage binary or BCD-decade up/down
counter with provisions for look-ahead carry in both counting modes. The
inputs consists of a single CLOCK, CARRY IN,(CLOCK ENABLE),
BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual
JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT signal are provided as
outputs.
A high PRESET ENABLE signal allows information on the JAM
INPUTS to preset the counter to any state asynchronously with the clock.
A low on each JAM line, when the PRESET-ENABLE signal is high, ORDERING INFORMATION
resets the counter to its zero count. The counter is advanced one count at
IW4029BN Plastic
the positive transition of the clock when the CARRY IN and PRESET
IW4029BD SOIC
ENABLE signals are low. Advancement is inhibited when the TA = -55° to 125° C for all packages
CARRY IN or PRESET ENABLE signals are high. The CARRY OUT
signal is normally high and goes low when the counter reaches its
maximum count in the UP mode or the minimum count in the DOWN
mode provided the CARRY IN signal is low. The CARRY IN signal in the low state can thus be considered a CLOCK
ENABLE. The CARRY IN terminal must be connected to GND when
not in use.
Binary counting is accomplished when the BINARY/DECADE
PIN ASSIGNMENT
input is high; the counter counts in the decade mode when the
BINARY/DECADE input is low. The counter counts up when the
UP/DOWN input is high, and down when the UP/DOWN input is low.
Parallel clocking provides synchronous control and hence faster
response from all counting outputs. Ripple-clocking allows for longer
clock input rise and fall times.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
LOGIC DIAGRAM
www.datasheet4u.com
PIN 16=VCC
PIN 8= GND
1
1 page  
IW4029B
TIMING REQUIREMENTS (CL=50pF, RL=200 kΩ, Input tr=tf=20 ns)
VCC Guaranteed Limit
Symbol
Parameter
V ≥-55°C 25°C ≤125°C
tw Minimum Pulse Width, Clock (Figure 1)
5.0 180 180 360
10 90
90 180
15 60
60 120
tw Minimum Pulse Width, Preset Enable
(Figure 1)
5.0 130 130 260
10 70
70 140
15 50
50 100
tsu* Minimum Setup Time, Clock to B/D or U/D 5.0 340 340 680
(Figure 1)
10 140 140 280
15 100 100 200
trem* Minimum Removal Time, Preset Enable (Figure 5.0 200 200 400
1) 10 110 110 220
15 80
80 160
th** Minimum Hold Time, Clock to Carry In (Figure 5.0 50
2) 10 30
15 25
50 100
30 60
25 50
tsu Minimum Setup Time, Carry In to Clock
(Figure 1)
5.0 200
10 70
15 60
200
70
60
tr, tf**
Maximum Input Rise and Fall Times,Clock
(Figure 2)
5.0 15
10 15
15 15
15
15
15
* From Up/Down, Binary/Decode, Carry In, or Preset Enable Control Inputs to Clock Edge.
** From Carry In to Clock Edge
400
140
120
30
30
30
Unit
ns
ns
ns
ns
ns
ns
µs
5
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet IW4029B.PDF ] | |
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