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PDF MK1493-02A Data sheet ( Hoja de datos )
| Número de pieza | MK1493-02A | |
| Descripción | Networking/pci Clock Generator | |
| Fabricantes | Integrated Circuit System | |
| Logotipo |  |
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MK1493-02A
Networking/PCI Clock Generator
Description
The MK1493-02A is a general purpose clock generator
that provides an integrated clocking solution for
PCI/Networking applications. It provides two pairs of
differential CPU clocks, four PCI clocks, seven PCI_X
clocks, two reference clocks, additional clock selectable
from REF/50 MHz, and six pairs of SSTL2 DDR at
2.5 V. All complementary outputs operate only from
a 2.5 V power supply.
Input/Output Features
• Packaged in 56-pin TSSOP package
• 2 - Pairs of differential CPU clocks (differential
current mode)
• 4 - PCI @ 3.3 V
• 7 - PCI_X @ 3.3 V
• 2 - REF @ 3.3 V, Fixed
• 6 - Pairs of differential SSTL2 DDR @ 2.5 V
• 1 - REF/50 MHz, selectable
• Spread spectrum for EMI control
• Supports SMBUS index read/write and blocks
read/write operations
• Uses external 25 or 50 MHz crystal or clock
• CPU output jitter <125 ps
• PCI cycle to cycle output jitter <250 ps
• DDR cycle to cycle output jitter <150 ps
Block Diagram
PLL2
50MHz/REF2
X1
External capacitor
required with crystal for
accurate timing of clock
XTAL
OSC
2 REF(0:1)
X2
PLL1
Spread
Spectrum
ww OE
w FREQSEL
FS (3:0)
.D SDATA
SCLK
a CLK_STOPB
ta PCI_STOPB
S SSEN
4
Control
Logic
Config.
Reg.
CPU
Divider
PCI
Divider
Stop
Stop
Delay
Delay
AGP
Divider
DDR
Divider
Stop
Stop
Delay
Delay
2
2
CPUCLKT (1:0)
CPUCLKC (1:0)
7 PCI_XCLK (6:0)
4 PCI (3:0)
6
6
DDRT (5:0)
DDRC (5:0)
IREF
heet4UMDS 1493-02A C
1
Revision 020204
.comIntegrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
1 page  
MK1493-02A
Networking/PCI Clock Generator
General SMBUS Serial Interface Info
General SM-Bus Serial Interface
Information
How to Write:
• Controller (host) sends a start bit
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the beginning byte location =
N
• ICS clock will acknowledge
• Controller sends Byte Count X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through Byte
N+X-1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
T starT
Slave
Address D2
WR
(H)
ACK
Beg Location = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
O
O
O
ACK
O
O
O
Byte N + X - 1
ACK
P stoP
How to Read:
• Controller (host) will send a start bit
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the beginning Byte location =
N
• ICS clock will acknowledge
• Controller (host) will send a repeat start bit
• Controller (host) sends the read address Byte D3 (H)
• ICS clock will acknowledge
• ICS clock will send the data Byte count = X
• ICS clock sends Byte N
• ICS clock sends Byte N+X-1
• Controller (host) will need to acknowledge each Byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Controller (Host)
ICS (Slave/Receiver)
T
Slave Address
D2 (H)
starT bit
WR
=0
ACK
Beginning Loc = N
ACK
RT repeat
starT
Slave Address
D2 (H)
RD
=1
ACK
Data Byte Count=X
ACK
ACK
O
O
O
Beginning Byte N
X
B
Y
O
TO
EO
S
Byte N + X - 1
N NAK
P stoP bit
MDS 1493-02A C
5
Revision 020204
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
5 Page 
MK1493-02A
Networking/PCI Clock Generator
Byte 13: Spread Spectrum Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SS 7
SS 6
SS 5
SS 4
SS 3
SS 2
SS 1
SS 0
PUP
X
X
X
X
X
X
X
X
Description
The Spread Spectrum (13:0) (or see Byte 14) bit will
program the spread percentage. Spread percent
needs to be calculated based on the VCO frequency,
spreading profile, spreading amount, and spread
frequency. It is recommended to use ICS software
forspread programming. Default power on is latched
FS divider.
Byte 14: Spread Spectrum Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
RESERVED
RESERVED
SS 13
SS 12
SS 11
SS 10
SS 9
SS 8
PUP
X
X
X
X
X
X
X
X
Description
RESERVED
RESERVED
Spread Spectrum Bit 13
Spread Spectrum Bit 12
Spread Spectrum Bit 11
Spread Spectrum Bit 10
Spread Spectrum Bit 9
Spread Spectrum Bit 8
Byte 15: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
DDR Div 3
DDR Div 2
DDR Div 1
DDR Div 0
CPU Div 3
CPU Div 2
CPU Div 1
CPU Div 0
PUP
X
X
X
X
X
X
X
X
Description
DDRC clock divider ratio can be configured via these
four bits individually. For divider selection table, refer
to Table 1. Default at power up is latched FS divider.
CPU clock divider ratio can be configured via these
four bits individually. For divider selection table refer
to Table 1. Default at power up is latched FS divider.
MDS 1493-02A C
11
Revision 020204
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet MK1493-02A.PDF ] | |
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