PDF AD6652 Data sheet ( Hoja de datos )

Número de pieza	AD6652
Descripción	12-Bit / 65 MSPS IF to Baseband Diversity Receiver
Fabricantes	Analog Devices
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No Preview Available ! 12-Bit, 65 MSPS IF to Baseband Diversity Receiver AD6652 FEATURES SNR = 90 dB in 150 kHz bandwidth (to Nyquist @ 61.44 MSPS) Worst harmonic = 83 dBc (to Nyquist @ 61.44 MSPS) Integrated dual-channel ADC: Sample rates up to 65 MSPS IF sampling frequencies to 200 MHz Internal ADC voltage reference Integrated ADC sample-and-hold inputs Flexible analog input range (1 V to 2 V p-p) Differential analog inputs ADC clock duty cycle stabilizer 85 dB channel isolation/crosstalk Integrated wideband digital downconverter (DDC): Crossbar switched DDC inputs Digital resampling for noninteger decimation Programmable decimating FIR filters Flexible control for multicarrier and phased array Dual AGC stages for output level control Dual 16-bit parallel or 8-bit link output ports User-configurable built-in self-test (BIST) capability Energy-saving power-down modes APPLICATIONS Communications Diversity radio systems Multimode digital receivers: GSM, EDGE, PHS, AMPS, UMTS, WCDMA, CDMA-ONE, IS95, IS136, CDMA2000, IMT-2000 I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications Instrumentation and test equipment FUNCTIONAL BLOCK DIAGRAM DUAL-CHANNEL 12-BIT A/D FRONT END WIDEBAND DIGITAL DOWNCONVERTER (DDC) VINA+ VINA– SHA REFTA REFBA VREF SENSE REFTB REFBB VINB+ VINB– SHA ADC 12 CHANNEL A CHANNEL / A OTRA LIA LIA VREF PSEUDO RANDOM NOISE SEQUENCE LIB LIB OTRB ADC 12 CHANNEL / B CHANNEL B RCIC2 RESAMPLER CIC5 NCO RCIC2 RESAMPLER CIC5 NCO RCIC2 RESAMPLER CIC5 NCO RCIC2 RESAMPLER CIC5 NCO RAM COEF. FILTER CHANNEL 0 RAM COEF. FILTER CHANNEL 1 RAM COEF. FILTER CHANNEL 2 RAM COEF. FILTER CHANNEL 3 TO OUTPUT PORTS RCF OUTPUTS CHANNELS 0, 1, 2, 3 TO OUTPUT PORTS AGC A* TO OUTPUT PORTS AGC B* TO OUTPUT PORTS RCF OUTPUTS CHANNELS 0, 1, 2, 3 PORT A 8-BIT DSP LINK OR 16-BIT PARALLEL OUTPUT CONTROL OUTPUT MUX CIRCUITRY PORT B 8-BIT DSP LINK OR 16-BIT PARALLEL OUTPUT PDWN SHRDREF MODE ACLK SELECT DUTYEN CLOCK DUTY CYCLE STABILIZER SYNCA SYNCB SYNCC SYNCD EXTERNAL SYNC. CIRCUIT *DATA INTERLEAVING AND INTERPOLATING HB FILTER CONTROL DDC CLK BUILT-IN SELF-TEST CIRCUITRY PROGRAM MICROPORT 8 33 +3.0AVDD +3.3VDDIO 2.5VDD AGND DGND CLK DATA CONT ADD Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. 1 page AD6652 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Table 1. Parameter AVDD VDD VDDIO TAMBIENT Temp Full Full Full Test Level IV IV IV IV Min 2.75 2.25 3.0 −40 Typ 3.0 2.5 3.3 +25 Max Unit 3.3 V 2.75 V 3.6 V +85 °C ADC DC SPECIFICATIONS AVDD = 3.0 V, VDD = 2.5 V, VDDIO = 3.3 V, 61.44 MSPS, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted. Table 2. Parameter (Conditions) RESOLUTION INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Load Regulation @ 1.0 mA Output Voltage Error (0.5 V Mode) Load Regulation @ 0.5 mA INPUT REFERRED NOISE Input Span = 1 V Internal Input Span = 2 V Internal ANALOG INPUT Input Span = 1.0 V Input Span = 2.0 V Input Capacitance REFERENCE INPUT RESISTANCE MATCHING CHARACTERISTICS Offset Error Gain Error Temp Full Full Full Full Full 25°C 25°C Full Full Full Full Full Full Test Level Min Typ Max Unit IV 12 Bits IV ±5 ±35 mV V 0.8 mV V ±2.5 mV V 0.1 mV V 0.54 LSB rms V 0.27 LSB rms IV 1 V p-p IV 2 V p-p V 7 pF V 7 kΩ V ±0.1 % FSR V ±0.1 % FSR ADC SWITCHING SPECIFICATIONS AVDD = 3.0 V, VDD = 2.5 V, VDDIO = 3.3 V, 61.44 MSPS, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted. Table 3. Parameter (Conditions) SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate ACLK Period ACLK Pulse Width High1 ACLK Pulse Width Low1 DATA OUTPUT PARAMETERS Wake-Up Time2 OUT-OF-RANGE RECOVERY TIME Temp Full Full Full Full Full Full Full Test Level Min IV 65 V V 15.4 V 6.2 V 6.2 V V Typ Max 1 ACLK/2 ACLK/2 2.5 2 Unit MSPS MSPS ns ns ns ms Cycles 1 Duty cycle stabilizer enabled. 2 Wake-up time is dependent on the value of decoupling capacitors, typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB. Rev. 0 \| Page 5 of 76 5 Page AD6652 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 9. BGA Pin Configuration (Top View) 1 2 3 4 5 6 7 8 9 10 A DGND PA7_LA7 A2 PA6_LA6 D1 D3 CS RESET MODE SYNCD B Do Not Connect PA4_LA4 PACH0_ LACLK OUT A0 DGND C PA9 PA3_LA3 A1 DS (RD) D0 D PA1_LA1 PA2_LA2 PACH1_ LACLKIN VDD VDD R/W (WR) D4 D2 D5 VDD VDD D6 D7 VDDIO SYNCC DTACK (RDY) VDDIO SYNCA SYNCB VDDIO E PA8 PA5_LA5 n.c. VDD VDD VDD VDD VDDIO VDDIO VDDIO F PA0_LA0 DGND PA10 DGND DGND DGND DGND DGND DGND DGND G PA12 PA11 PA13 DGND DGND DGND DGND DGND DGND DGND H PAREQ PA15 PA14 DGND DGND DGND DGND DGND DGND DGND J CHIP_ID1 DGND DGND DGND DGND DGND DGND DGND DGND DGND K CHIP_ID3 PAACK CHIP_ID0 DGND DGND DGND DGND DGND DGND DGND L PB6_LB6 PB7_LB7 DGND DGND DGND DGND DGND DGND DGND DGND M CHIP_ID2 PB3_LB3 PB4_LB4 VDDIO VDDIO VDDIO VDDIO VDD VDD VDD N PAIQ PBCH1_ LBCLK IN PB2_LB2 VDDIO VDDIO VDDIO VDDIO VDD VDD VDD P DGND PB0_LB0 PB8 PB10 PB14 VDDIO PBACK LIB n.c. n.c. R PBIQ PBCH0_L BCLKOUT PB1_ LB1 PB9 PB12 PB15 n.c. n.c. n.c. n.c. T DGND PCLK PB5_ LB5 PB11 PB13 PBREQ n.c. n.c. n.c. n.c. 11 OTRA LIA LIA VDDIO VDDIO DGND DGND DGND DGND DGND DGND VDD VDD OTRB n.c. DCLK 12 PDWN 13 AVDD DUTYEN AVDD LIB AVDD VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD VDDIO AVDD n.c. AVDD PDWN AVDD SHRDREF AVDD 14 AVDD AVDD AVDD AVDD AVDD AGND AGND AGND AGND AGND AGND AVDD AVDD AVDD AVDD ACLK 15 AGND AGND AGND AGND AGND AGND REFBB AGND AGND REFBA AGND AGND AGND AGND AGND AGND 16 AGND AGND VIN+B VIN−B AGND AGND REFTB SENSE VREF REFTA AGND AGND VIN−A VIN+A AGND AGND Rev. 0 \| Page 11 of 76 11 Page

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