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PDF KM29W32000TS Data sheet ( Hoja de datos )
| Número de pieza | KM29W32000TS | |
| Descripción | 4M x 8-Bit NAND Flash Memory | |
| Fabricantes | Samsung Semiconductor | |
| Logotipo |  |
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.comKM29W32000TS
t4UDocument Title
ee4M x 8 Bit NAND Flash Memory
taShRevision History
.DaRevision No. History
w 0.0 Initial issue.
ww 1.0 Data Sheet, 1998
FLASH MEMORY
Draft Date
April 10th 1998
July 14th 1998
Remark
Preliminary
Final
1.1 Data Sheet, 1999
www.DataSheet4U.com1) Added CE dont’ care mode during the data-loading and reading
April 10th 1999
Final
eet4U.comThe attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
hto change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
Sany questions, please contact the SAMSUNG branch office near you.
www.Data1
1 page  
KM29W32000TS
FLASH MEMORY
PIN DESCRIPTION
Command Latch Enable(CLE)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the path activation for address and input data to the internal address/data register.
Addresses are latched on the rising edge of WE with ALE high, and input data is latched when ALE is low.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to standby
mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge
of RE which also increments the internal column address counter by one.
Spare Area Enable(SE)
The SE input controls the spare area selection when SE is high, the device is deselected the spare area during Read1, Sequential
data input and page Program.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
Power Line(VCC & VCCQ)
The VCCQ is the power supply for I/O interface logic. It is electrically isolated from main power line(VCC=2.7~5.5V) for supporting 5V
tolerant I/O with 5V power supply at VCCQ.
5
5 Page 
KM29W32000TS
* Command Latch Cycle
CLE
CE
WE
ALE
I/O0~7
tCLS
tCS
tCLH
tCH
tWP
tALS
tALH
tDS tDH
Command
FLASH MEMORY
* Address Latch Cycle
CLE
CE
WE
ALE
I/O0~7
tCLS
tCS tWC tWC
tALS
tWP
tWH
tWP
tWH
tWP
tALH
tDS tDH
A0~A7
tDS tDH
A9~A16
tDS tDH
A17~A21
11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet KM29W32000TS.PDF ] | |
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