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PDF AT8985P Data sheet ( Hoja de datos )
| Número de pieza | AT8985P | |
| Descripción | 6 Port 10/100 Mb/s Single Chip Ethernet Switch Controller | |
| Fabricantes | ATAN | |
| Logotipo |  |
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ATAN Technology, Inc.
AT8985P 6 port 10/100 Mb/s
Single Chip Ethernet Switch Controller
Preliminary Data Sheet
Revision 1.0
Feb 2002
6 port 10/100Mb/s Single Chip Switch Controller
1
Revision 1.0
AT8985P
1 page  
ATAN Technology, Inc.
2. Pinout
2.1 5 TP/FX PORT+ MII PORT 128 Pin Diagram
103 DUPCOL4
104 GNDO
105 VCC3O
106 DUPCOL3
107 DUPCOL2
108 DUPCOL1 (PHYAS1)
109 DUPCOL0 (RECANEN)
110 VCC2IK
111 GNDIK
112 RC
113 XI
114 XO
115 VCCPLL
116 GNDPLL
117 CONTROL
118 VREF
119 GNDBIAS
120 RTX
121 VCCBIAS
122 VCCA2
123 TXP0
124 TXN0
125 GNDA
126 RXP0
127 RXN0
128 VCCAD
AT8985P-128
GNDIK
(GFCEN) TXD0
(P4FX) TXER
TXD1
TXD2
TXD3
LDSPD4
GNDO
VCC3O
LDSPD3
LDSPD2
VCC2IK
GNDIK
LDSPD1
LDSPD0
TEST
VCC2IK
GNDIK
GNDSUBA
VCCA2
TXP4
TXN4
GNDA
RXP4
RXN4
VCCAD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
6 port 10/100Mb/s Single Chip Switch Controller
5
Revision 1.0
AT8985P
5 Page 
ATAN Technology, Inc.
3.2.2.2 Adaptive Equalizer and timing Recovery Module
All digital design is especial immune from noise environments and achieves better correlation between production and
system testing. Baud rate Adaptive Equalizer/Timing Recovery compensates line loss induced from twisted pair and
tracks far end clock at 125M samples per second. Adaptive Equalizer implemented with Feed forward and Decision
Feedback techniques meet the requirement of BER less than 10-12 for transmission on CAT5 twisted pair cable ranging
from 0 to 120 meters.
3.2.2.3 NRZI/NRZ and Serial/Parallel Decoder
The recovered data is converted from NRZI to NRZ. The data is not necessarily aligned to 4B/5B code group’s boundary.
3.2.2.4 Data De-scrambling
The de-scrambler acquires synchronization with the data stream by recognizing idle bursts of 40 or more bits and locking
its deciphering Linear Feedback Shift Register (LFSR) to the state of the scrambling LFSR. Upon achieving
synchronization, the incoming data is XORed by the deciphering LFSR and de-scrambled.
In order to maintain synchronization, the de-scrambler continuously monitors the validity of the unscrambled data that it
generates. To ensure this, a link state monitor and a hold timer are used to constantly monitor the synchronization status.
Upon synchronization of the de-scrambler the hold timer starts a 722 us countdown. Upon detection of sufficient idle
symbols within the 722 us period, the hold timer will reset and begin a new countdown. This monitoring operation will
continue indefinitely given a properly operating network connection with good signal integrity. If the link state monitor
does not recognize sufficient unscrambled idle symbols within 722 us period, the de-scrambler will be forced out of the
current state of synchronization and reset in order to re-acquire synchronization.
3.2.2.5 Symbol Alignment
The symbol alignment circuit in the AT8985P determines code word alignment by recognizing the /J/K delimiter pair.
This circuit operates on unaligned data from the de-scrambler. Once the /J/K symbol pair (11000 10001) is detected,
subsequent data is aligned on a fixed boundary.
3.2.2.6 Symbol Decoding
The symbol decoder functions as a look-up table that translates incoming 5B symbols into 4B nibbles as shown in Table 1.
The symbol decoder first detects the /J/K symbol pair preceded by idle symbols and replaces the symbol with MAC
preamble. All subsequent 5B symbols are converted to the corresponding 4B nibbles for the duration of the entire packet.
This conversion ceases upon the detection of the /T/R symbol pair denoting the end of stream delimiter (ESD). The
translated data is presented on the internal RXD[3:0] signal lines with RXD[0] represents the least significant bit of the
translated nibble.
3.2.2.7 Valid Data Signal
The valid data signal (RXDV) indicates that recovered and decoded nibbles are being presented on the internal RXD[3:0]
synchronous to receive clock, RXCLK. RXDV is asserted when the first nibble of translated /J/K is ready for transfer
over the internal MII. It remains active until either the /T/R delimiter is recognized, link test indicates failure, or no signal
is detected. On any of these conditions, RXDV is de-asserted.
6 port 10/100Mb/s Single Chip Switch Controller
11
Revision 1.0
AT8985P
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT8985P.PDF ] | |
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