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UC2843A fiches techniques PDF

ST Microelectronics - (UC2842A - UC2845A) HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER

Numéro de référence UC2843A
Description (UC2842A - UC2845A) HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER
Fabricant ST Microelectronics 
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UC2843A fiche technique
UC284XA
UC384XA
HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER
NOT FOR NEW DESIGN
1 FEATURES
Figure 1. Package
TRIMMED OSCILLATOR DISCHARGE
CURRENT
CURRENT MODE OPERATION TO 500kHz
AUTOMATIC FEED FORWARD
COMPENSATION
DIP-8
SO-8
LATCHING PWM FOR CYCLE-BY-CYCLE
CURRENT LIMITING
Table 1. Order Codes
INTERNALLY TRIMMED REFERENCE WITH
Part Number
Package
UNDERVOLTAGE LOCKOUT
HIGH CURRENT TOTEM POLE OUTPUT
t(s)UNDERVOLTAGE LOCKOUT WITH
HYSTERESIS
cLOW START-UP CURRENT (< 0.5mA)
uDOUBLE PULSE SUPPRESSION
rod2 DESCRIPTION
PThe UC384xA family of control ICs provides the
necessary features to implement off-line or DC to
teDC fixed frequency current mode control schemes
lewith a minimal external parts count. Internally im-
oplemented circuits include a trimmed oscillator for
sprecise DUTY CYCLE CONTROL under voltage
blockout featuring start-up current less than 0.5mA,
Oa precision reference trimmed for accuracy at the
-error amp input, logic to insure latched operation,
)a PWM comparator which also provides current
t(slimit control, and a totem pole output stage de-
csigned to source or sink high peak current. The
uoutput stage, suitable for driving N-Channel MOS-
dFETs, is low in the off-state.
UC2842AD1; UC3842AD1;
UC2843AD1; UC3843AD1;
UC2844AD1; UC3844AD1;
UC2845AD1; UC3845AD1
UC2842AN; UC3842AN;
UC2843AN; UC3843AN;
UC2844AN; UC3844AN;
UC2845AN; UC3845AN
SO-8
DIP-8
Differences between members of this family are
the under-voltage lockout thresholds and maxi-
mum duty cycle ranges. The UC3842A and
UC3844A have UVLO thresholds of 16V (on) and
10V (off), ideally suited off-line applications The
corresponding thresholds for the UC3843A and
UC3845A are 8.5 V and 7.9V. The UC3842A and
UC3843A can operate to duty cycles approaching
100%. A range of the zero to < 50 % is obtained by
the UC3844A and UC3845A by the addition of an
internal toggle flip flop which blanks the output off
every other clock cycle.
ProFigure 2. Block Diagram (toggle flip flop used only in UC3844A and UC3845A)
te 7
Vi
le 5
Obso GROUND
34V
UVLO
2.50V
S/R
5V
REF
VREF GOOD
INTERNAL
BIAS
8 VREF
5V 50mA
LOGIC
6
OUTPUT
4
RT/CT
OSC
T
VFB
COMP
CURRENT
SENSE
2
1
3
ERROR AMP.
+
-
2R
R
S
R
1V
CURRENT
SENSE
COMPARATOR
PWM
LATCH
D95IN331
May 2004
REV. 5
1/16

PagesPages 16
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