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PDF EX256-xxx Data sheet ( Hoja de datos )
| Número de pieza | EX256-xxx | |
| Descripción | eX Family FPGAs | |
| Fabricantes | Actel | |
| Logotipo |  |
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eX Family FPGAs
v4.2
FuseLock
Leading Edge Performance
• 240 MHz System Performance
• 350 MHz Internal Performance
• 3.9 ns Clock-to-Out (Pad-to-Pad)
Specifications
• 3,000 to 12,000 Available System Gates
• Maximum 512 Flip-Flops (Using CC Macros)
• 0.22µm CMOS Process Technology
• Up to 132 User-Programmable I/O Pins
Features
• High-Performance, Low-Power Antifuse FPGA
• LP/Sleep Mode for Additional Power Savings
• Advanced Small-Footprint Packages
• Hot-Swap Compliant I/Os
• Single-Chip Solution
• Nonvolatile
• Live on Power-Up
• No Power-Up/Down Sequence Required for Supply
Voltages
• Configurable Weak-Resistor Pull-Up or Pull-Down
for Tristated Outputs during Power-Up
• Individual Output Slew Rate Control
• 2.5V, 3.3V, and 5.0V Mixed-Voltage Operation
with 5.0V Input Tolerance and 5.0V Drive Strength
• Software Design Support with Actel Designer and
Libero™ Integrated Design Environment (IDE)
Tools
• Up to 100% Resource Utilization with 100% Pin
Locking
• Deterministic Timing
• Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
• Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
• Fuselock™ Secure Programming Technology
Prevents Reverse Engineering and Design Theft
Product Profile
Device
eX64
eX128
Capacity
System Gates
Typical Gates
3,000
2,000
6,000
4,000
Register Cells
Dedicated Flip-Flops
Maximum Flip-Flops
64 128
128 256
Combinatorial Cells
128 256
Maximum User I/Os
84 100
Global Clocks
Hardwired
Routed
11
22
Speed Grades
–F, Std, –P
–F, Std, –P
Temperature Grades*
C, I, A
C, I, A
Package (by pin count)
TQFP
CSP
64, 100
49, 128
64, 100
49, 128
Note: *Refer to the eX Automotive Family FPGAs datasheet for details on automotive temperature offerings.
eX256
12,000
8,000
256
512
512
132
1
2
–F, Std, –P
C, I, A
100
128, 180
June 2004
© 2004 Actel Corporation
i
1 page  
eX Family FPGAs
eX Family FPGAs
General Description
The eX family of FPGAs is a low-cost solution for low-
power, high-performance designs. The inherent low
power attributes of the antifuse technology, coupled
with an additional low static power mode, make these
devices ideal for power-sensitive applications. Fabricated
with an advanced 0.22µm CMOS antifuse technology,
these devices achieve high performance with no power
penalty.
eX Family Architecture
Actel's eX family is implemented on a high-voltage twin-
well CMOS process using 0.22µm design rules. The eX
family architecture uses a “sea-of-modules” structure
where the entire floor of the device is covered with a
grid of logic modules with virtually no chip area lost to
interconnect elements or routing. Interconnection
among these logic modules is achieved using Actel’s
patented metal-to-metal programmable antifuse
interconnect elements. The antifuse interconnect is
made up of a combination of amorphous silicon and
dielectric material with barrier metals and has an "on"
state resistance of 25Ω with a capacitance of 1.0fF for
low-signal impedance. The antifuses are normally open
circuit and, when programmed, form a permanent low-
impedance connection. Actel’s eX family provides two
types of logic modules, the register cell (R-cell) and the
combinatorial cell (C-cell).
The R-cell contains a flip-flop featuring asynchronous
clear, asynchronous preset, and clock enable (using the
S0 and S1 lines) control signals (Figure 1-1). The R-cell
registers feature programmable clock polarity selectable
on a register-by-register basis. This provides additional
flexibility while allowing mapping of synthesized
functions into the eX FPGA. The clock source for the R-
cell can be chosen from either the hard-wired clock or
the routed clock.
The C-cell implements a range of combinatorial functions
up to five inputs (Figure 1-2 on page 1-2). Inclusion of
the DB input and its associated inverter function enables
the implementation of more than 4,000 combinatorial
functions in the eX architecture in a single module.
Two C-cells can be combined together to create a flip-
flop to imitate an R-cell via the use of the CC macro. This
is particularly useful when implementing non-timing-
critical paths and when the design engineer is running
out of R-cells. More information about the CC macro can
be found in Actel’s Maximizing Logic Utilization in eX, SX
and SX-A FPGA Devices Using CC Macros application
note.
Routed
Data Input S1
S0
DirectConnect
Input
PSET
DQ
Y
Figure 1-1 • R-Cell
HCLK
CLKA,
CLKB,
Internal Logic
CKS
CLR
CKP
v4.2
1-1
5 Page 
Figure 1-8 to Figure 1-11 on page 1-8 show some sample power characteristics of eX devices.
eX Family FPGAs
300
250
200
150
100
50
0
50
eX64
eX128
eX256
100 150 200
Frequency (MHz)
Notes:
1. Device filled with 16-bit counters.
2. VCCA, VCCI = 2.7V, device tested at room temperature.
Figure 1-8 • eX Dynamic Power Consumption – High Frequency
80
70
60
50
40
30
20
10
0
0
10 20 30 40
Frequency (MHz)
Notes:
1. Device filled with 16-bit counters.
2. VCCA, VCCI = 2.7V, device tested at room temperature.
Figure 1-9 • eX Dynamic Power Consumption – Low Frequency
50
eX64
eX128
eX256
v4.2
1-7
11 Page | ||
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| PDF Descargar | [ Datasheet EX256-xxx.PDF ] | |
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