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PDF NT256D64S8HA0G-6 Data sheet ( Hoja de datos )
| Número de pieza | NT256D64S8HA0G-6 | |
| Descripción | 256MB DIMM | |
| Fabricantes | Nanya Technology | |
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NT256D64S8HA0G-6
256MB : 32M x 64
omPC2700 Unbuffered DIMM
U.c184pin Two Bank Unbuffered DDR SDRAM MODULE Based on DDR333 16Mx8 SDRAM
eet4Features
h• 184-Pin Unbuffered 8-Byte Dual In-Line Memory Module
S• 32Mx64 Double Data Rate (DDR) SDRAM DIMM
ta• Performance :
a PC2700
.DSpeed Sort
-6 Unit
wDIMM CAS Latency
2.5 2
wf CK Clock Frequency
166 133 MHz
w t CK Clock Cycle
6 7.5 ns
• DRAM DLL aligns DQ and DQS transitions with clock transitions.
Also aligns QFC transitions with clock during Read cycles
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM CAS Latency: 2, 2.5
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
f DQ DQ Burst Frequency
333
266 MHz
• Intended for 166 MHz and 133 MHz applications
• Inputs and outputs are SSTL-2 compatible
m• VDD = 2.5Volt ± 0.2, VDDQ = 2.5Volt ± 0.2
o• Single Pulsed RAS interface
• SDRAMs have 4 internal banks for concurrent operation
.c• Module has two physical banks
• Differential clock inputs
• Data is read or written on both clock edges
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 12/10/2 Addressing (row/column/bank)
• 15.6 µs Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• SDRAMs in 66-pin TSOP Type II Package
t4UDescription
NT256D64S8HA0G-6 is an unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),
eorganized as a dual-bank high-speed memory array. The 32Mx64 module is a two-bank DIMM that uses sixteen 16Mx8 DDR
eSDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 333MHz. The DIMM is intended for use
hin applications operating from 133 MHz to 166 MHz clock speeds with data rates of 266 to 333 MHz. Clock enable CKE0 and / or CKE1
Scontrols all devices on the DIMM.
taPrior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by
address inputs A0-A11 and I/O inputs BA0 and BA1 using the mode register set cycle.
aThese DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common
design files minimizes electrical variation between suppliers.
.DThe DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD
data are programmed and locked during module assembly. The last 128 bytes are available to the customer.
wAll NANYA 184 DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.
wwOrdering Information
Part Number
NT256D64S8HA0G-6
Preliminary, 11/2001
Speed
166MHz (7ns @ CL = 2.5 )
133MHz (7.5ns @ CL= 2 )
.comPC2700
Organization
32Mx64
Leads
Gold
Power
2.5V
w.DataSheet4U1
w © NANYA TECHNOLOGY CORP.
wNANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
1 page  
NT256D64S8HA0G-6
256MB : 32M x 64
PC2700 Unbuffered DIMM
Absolute Maximum Ratings
Symbol
Parameter
Rating
Units
VIN, VOUT
Voltage on I/O pins relative to Vss
-0.5 to VDDQ+0.5
V
VIN Voltage on Input relative to Vss
-0.5 to +3.6
V
VDD Voltage on VDD supply relative to Vss
-0.5 to +3.6
V
VDDQ
Voltage on VDDQ supply relative to Vss
-0.5 to +3.6
V
TA Operating Temperature (Ambient)
0 to+70
°C
TSTG
Storage Temperature (Plastic)
-55 to +150
°C
PD Power Dissipation
16 W
IOUT
Short Circuit Output Current
50 mA
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Capacitance
Parameter
Symbol
Max.
Units
Notes
Input Capacitance: CK0, CK0 , CK1, CK1 , CK2, CK2
CI1 24 pF
1
Input Capacitance: A0-A11, BA0, BA1, WE , RAS , CAS
CI2 60 pF
1
Input Capacitance: CKE0, CKE1, S0 , S1
CI3 30 pF
1
Input/Output Capacitance DQ0-63; DQS0-7, 9-16
CIO1
14
pF 1,2
1. VDDQ = VDD = 2.5V ± 0.2V, f = 100 MHz, T A = 25 °C, V OUT (DC) = VDDQ/2 , VOUT (Peak to Peak) = 0.2V.
2. DQS inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at
the board level.
Preliminary, 11/2001
5
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
5 Page 
NT256D64S8HA0G-6
256MB : 32M x 64
PC2700 Unbuffered DIMM
Serial Presence Detect
Byte Description
SPD Entry Value
-6
0 Number of Serial PD Bytes Written during Production
128
1 Total Number of Bytes in Serial PD device
256
2 Fundamental Memory Type
SDRAM DDR
3 Number of Row Addresses on Assembly
12
4 Number of Column Addresses on Assembly
10
5 Number of DIMM Bank
2
6. Data Width of Assembly
X64
7 Data Width of Assembly (cont’)
X64
8 Voltage Interface Level of this Assembly
SSTL 2.5V
9 SDRAM Device Cycle Time at CL=2.5
6ns
10 SDRAM Device Access Time from Clock at CL=2.5
0.7ns
11 DIMM Configuration Type
Non-Parity
12 Refresh Rate/Type
15.6µs / SR
13 Primary SDRAM Width
X8
14 Error Checking SDRAM Device Width
N/A
SDRAM Device Attributes :
15
Minimum Clock Delay, Random Column Access
1 Clock
16 SDRAM Device Attributes: Burst Length Supported
2,4,8
17 SDRAM Device Attributes: Number of Device Banks
4
18 SDRAM Device Attributes: CAS Latency
2, 2.5
19 SDRAM Device Attributes: CS Latency
0
20 SDRAM Device Attributes: WE Latency
1
21 SDRAM Module Attributes
Differential Clock
22 SDRAM Device Attributes: General
+/-0.2V Voltage Tolerance
23 Minimum Clock Cycle at CL=2
7.5ns
24 Maximum Data Access Time from Clock at CL=2
± 0.7ns
25 Minimum Clock Cycle Time at CL=1
N/A
26 Maximum Data Access Time from Clock at CL=1
N/A
27 Minimum Row Precharge Time (tRP)
18ns
28 Minimum Row Active to Row Active delay (tRRD)
12ns
29 Minimum RAS to CAS delay (tRCD)
18ns
30 Minimum RAS Pulse Width (tRAS)
42ns
31 Module Bank Density
128MB
32 Address and Command Setup Time Before Clock
0.75ns
33 Address and Command Hold Time After Clock
0.75ns
34 Data Input Setup Time Before Clock
0.45ns
35 Data Input Hold Time After Clock
0.45ns
36-61 Reserved
Undefined
62 SPD Revision
0
63 Checksum Data
64-71 Manufacturer’s JEDED ID Code
NANYA
72 Module Manufacturing Location
N/A
73-90 Module Part number
N/A N/A N/A
91-92 Module Revision Code
N/A
93-94 Module Manufacturing Data
Year / Week Code
95-98 Module Serial Number
Serial Number
99-255 Reserved
Undefined
1. yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex)
2. ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex)
Serial PD Data Entry
(Hexadecimal)
-6
80
08
07
0C
0A
02
40
00
04
60
70
00
80
08
00
01
0E
04
0C
01
02
20
00
75
70
00
00
48
30
48
2A
20
75
75
45
45
00
00
E8
7F7F7F0B00000000
00
00 00 00
00
yy/ww
00
00
Note
1,2
Preliminary, 11/2001
11
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
11 Page | ||
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