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PDF AT89S8253 Data sheet ( Hoja de datos )
| Número de pieza | AT89S8253 | |
| Descripción | 8-Bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Compatible with MCS®51 Products
• 12K Bytes of In-System Programmable (ISP) Flash Program Memory
– SPI Serial Interface for Program Downloading
– Endurance: 10,000 Write/Erase Cycles
• 2K Bytes EEPROM Data Memory
– Endurance: 100,000 Write/Erase Cycles
• 64-byte User Signature Array
• 2.7V to 5.5V Operating Range
• Fully Static Operation: 0 Hz to 24 MHz (in x1 and x2 Modes)
• Three-level Program Memory Lock
• 256 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Three 16-bit Timer/Counters
• Nine Interrupt Sources
• Enhanced UART Serial Port with Framing Error Detection and Automatic
Address Recognition
• Enhanced SPI (Double Write/Read Buffered) Serial Interface
• Low-power Idle and Power-down Modes
• Interrupt Recovery from Power-down Mode
• Programmable Watchdog Timer
• Dual Data Pointer
• Power-off Flag
• Flexible ISP Programming (Byte and Page Modes)
– Page Mode: 64 Bytes/Page for Code Memory, 32 Bytes/Page for Data Memory
• Four-level Enhanced Interrupt Controller
• Programmable and Fuseable x2 Clock Option
• Internal Power-on Reset
• 42-pin PDIP Package Option for Reduced EMC Emission
• Green (Pb/Halide-free) Packaging Option
8-bit
Microcontroller
with 12 Kbyte
Flash
AT89S8253
1. Description
The AT89S8253 is a low-power, high-performance CMOS 8-bit microcontroller with
12K bytes of In-System Programmable (ISP) Flash program memory and 2K bytes of
EEPROM data memory. The device is manufactured using Atmel’s high-density non-
volatile memory technology and is compatible with the industry-standard MCS-51
instruction set and pinout. The on-chip downloadable Flash allows the program mem-
ory to be reprogrammed in-system through an SPI serial interface or by a
conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU
with downloadable Flash on a monolithic chip, the Atmel AT89S8253 is a powerful
microcontroller which provides a highly-flexible and cost-effective solution to many
embedded control applications.
3286P–MICRO–3/10
1 page  
AT89S8253
3.9 Port 3
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can
sink/source six TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the weak
internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being
pulled low will source current (IIL,150 µA typical) because of the weak internal pull-ups.
Port 3 receives some control signals for Flash programming and verification.
Port 3 also serves the functions of various special features of the AT89S8253, as shown in the
following table.
Port Pin
Alternate Functions
P3.0
RXD (serial input port)
P3.1
P3.2
P3.3
TXD (serial output port)
INT0 (external interrupt 0)(1)
INT1 (external interrupt 1)(1)
P3.4
T0 (timer 0 external input)
P3.5
T1 (timer 1 external input)
P3.6
WR (external data memory write strobe)
P3.7
RD (external data memory read strobe)
Note:
1. All pins in ports 1 and 2 and almost all pins in port 3 (the exceptions are P3.2 INT0 and P3.3
INT1) have their inputs disabled in the Power-down mode. Port pins P3.2 (INT0) and P3.3
(INT1) are active even in Power-down mode (to be able to sense an interrupt request to exit
the Power-down mode) and as such still have their weak internal pull-ups turned on.
3.10 RST
Reset input. A high on this pin for at least two machine cycles while the oscillator is running
resets the device.
3.11 ALE/PROG
Address Latch Enable. ALE/PROG is an output pulse for latching the low byte of the address (on
its falling edge) during accesses to external memory. This pin is also the program pulse input
(PROG) during Flash programming.
In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be
used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur-
ing each access to external data memory.
If desired, ALE operation can be disabled by setting bit 0 of the AUXR SFR at location 8EH. With
the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly
pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execu-
tion mode.
3.12 PSEN
Program Store Enable. PSEN is the read strobe to external program memory (active low).
When the AT89S8253 is executing code from external program memory, PSEN is activated
twice each machine cycle, except that two PSEN activations are skipped during each access to
external data memory.
3286P–MICRO–3/10
5
5 Page 
AT89S8253
7. Power-On Reset
A Power-On Reset (POR) is generated by an on-chip detection circuit. The detection level is
nominally 1.4V. The POR is activated whenever VCC is below the detection level. The POR cir-
cuit can be used to trigger the start-up reset or to detect a supply voltage failure in devices
without a brown-out detector. The POR circuit ensures that the device is reset from power-on.
When VCC reaches the Power-on Reset threshold voltage, the POR delay counter determines
how long the device is kept in POR after VCC rise, nominally 2 ms. The POR signal is activated
again, without any delay, when VCC falls below the POR threshold level. A Power-On Reset (i.e.
a cold reset) will set the POF flag in PCON.
Figure 7-1. Power-up and Brown-out Detection Sequence
VCC
Min VCC Level 2.7V
BOD Level 2.3V
POR Level 1.4V
POR
t
XTAL1
2.4V
WRTINH
Internal
RESET
0
tPOR
(2 ms)
1.2V
tPOR
(2 ms)
t
t
t
t
7.1 Memory Brown-out Protection
The AT89S8253 has an on-chip Brown-out Detection (BOD) circuit for monitoring the VCC level
during operation by comparing it to a fixed trigger level of nominally 2.2V (2.4V max). The pur-
pose of the BOD is to ensure that if VCC fails or dips, the Flash or EEPROM memories cannot be
erased/written at voltages too low for programming. At powerup the VCC level must pass the
BOD threshold before execution starts. When VCC decreases to a value below the trigger level,
the WRTINH bit in EECON is activated and futher programming of the Flash/EEPROM is
restricted. When VCC increases above the trigger level, the BOD delay counter blocks program-
ming until after the timeout period has expired in approximately 2 ms. The BOD does not reset
the system as shown in Figure 7-1. To protect the system from errors induced by incorrect exe-
cution at lower voltages an external BOD circuit may be required.
3286P–MICRO–3/10
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT89S8253.PDF ] | |
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