PDF STA002 Data sheet ( Hoja de datos )

Número de pieza	STA002
Descripción	STARMANO CHANNEL DECODER
Fabricantes	ST Microelectronics
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No Preview Available ! ® STA002 STARMAN™ CHANNEL DECODER FRONT_END INTERFACE: IF input carrier frequency: f = 1.84 MHz Single internal 6 bit A/D converter QPSK demodulation Input symbol frequency: Fs = 1.84 Msymbols/s Digital Nyquist root filter: - roll-off value of 0.4 Digital carrier loop: - on-chip quadrature demodulator and tracking loop - lock detector - C/N indicator Digital timing recovery: - internal timing error evaluation, filter and correction Digital AGC: - internal signal power estimation and filter - output control signal for AGC (1 bit PWM) FORWARD ERROR CORRECTION: Inner decoder: - Viterbi soft decoder for convolutional codes, constraint length M=7, Rate 1/2 Deinterleaver block Outer decoder: - Reed-Solomon decoder for 32 parity bytes; correction of up to 16 byte errors - Block lengths: 255 - Energy dispersal descrambler BACK_END INTERFACE: Broadcast Channel selection Audio Service Component selection to MPEG decoder Service Component selection CONTROL: I2C serial Bus control interface TQFP44 DECRYPTION: WES scheme supported DESCRIPTION Designed for World Space satellites digital audio receivers, the STA002 Digital Receiver Front-end integrates all the blocks needed to demodulate incoming digital satellite audio signals from the tuner: analog to digital converter, QPSK demodu- lator, signal power estimator, automatic gain con- trol, Viterbi decoder, deinterleaver, Reed-Solo- mon decoder and energy dispersal descrabler. Its advanced error correction functions guarantees a low error rate even with small low gain receiver antennas. Additional functions include the selection of broadcast channel, service components and audio components for source decoding: - The MPEG Audio bitstream is provided at the serial audio output port. - The Broadcast Channel is provided to the serial data output port. - The Service Component is provided at the SC output interface. World Space encryption scheme is supported for pay programs and paging. www.DataSheet4U.com January 2002 1/43 www.DataSheet4U.com 1 page Fig. 3: Test Circuit STA002 VDD 100nF VDD 100nF VDD 100nF VDD 100nF VDD 100nF VDD 100nF AVDD TEST1 RXI NRXI M_CLK TEST_CLK TEST2 3 8 14 17 21 19 26 30 38 35 40 42 4 7 1 5 6 9 10 11 44 34 33 32 25 23 22 20 16 15 12 200 43 200 41 200 39 200 37 200 36 200 31 200 29 200 28 200 27 200 24 200 18 200 2 200 13 TEST9 TEST8 TEST7 BCDIN TEST6 TEST5 TEST4 RESET SCL SDA TEST3 SCDI SCCK SEN BCDO BCCK BCSYNC SDI SCK SEN MINTR INTR AGC LOCK VDD 4.7µF 100nF VSS 4.7µF 100nF VSS 100nF 100nF 100nF VSS AVDD 4.7µF 100nF AVSS 4.7µF 100nF AVSS 100nF 100nF 100nF AVSS D99AU1011 Figure 4. Test Load Circuit VDD IOL OUTPUT CL IOH VREF D98AU967 Test Load Output SDA Other Outputs IOL 5mA 100µA IOH 100µA CL 100pF 100pF VREF 3.6V 1.5V 5/43 5 Page 1.5.3 QPSK Registers HEX_COD DEC_COD REGISTER NAME 080H 081H 082H 083H 084H 085H 086H 087H 088H 089H 08AH 08BH 08CH 08DH 08EH 08FH 090H 091H 092H 093H 094H 095H 096H 097H 098H 099H 09AH 09BH 09CH 09DH 09EH 09FH 128 QPSK_CONTROL1 129 QPSK_CONTROL2 130 AGC1 _REF1 (note 1) 131 AGC1 _REF2 (note 1) 132 AGC1_BETA 133 AGC1_INTG 134 AGC2 _REF 135 AGC2 _BETA 136 AGC2_INTG 137 CN_CNT 138 SYMFREQ1 (note 1) 139 SYMFREQ2 (note 1) 140 SYMFREQ3 (note 1) 141 TIMFLTPAR 142 TIMINTG 143 CARFLTPAR 144 IFFREQ1 (note 1) 145 IFFREQ2 (note 1) 146 IFFREQ3 (note 1) 147 IFFREQ4 (note 1) 148 CARINTG 149 RAMPCTRL 150 CARFREQ1 151 CARFREQ2 152 CARFREQ3 153 FLAG 154 RFU 155 RFU 156 RFU 157 RFU 158 RFU 159 RFU Note 1: when updated all bytes must be written STA002 TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R RESET VALUE 10H 90H 06H 01H 00H 7FH 16H 00H 23H FFH D3H 11H 0CH 48H 00H 57H 37H 1DH C1H 00H 00H 01H 11/43 11 Page

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