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STP10NC50FP fiches techniques PDF

ST Microelectronics - N-CHANNEL Power MOSFET

Numéro de référence STP10NC50FP
Description N-CHANNEL Power MOSFET
Fabricant ST Microelectronics 
Logo ST Microelectronics 





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STP10NC50FP fiche technique
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STP10NC50
® STP10NC50FP
N - CHANNEL 500V - 0.48- 10A - TO-220/TO-220FP
PowerMESHMOSFET
PRELIMINARY DATA
TYPE
VDSS
RDS(on)
ID
ST P10 NC5 0
500 V
STP10NC50FP 500 V
< 0.52
< 0.52
10 A
10 A
s TYPICAL RDS(on) = 0.48
s EXTREMELY HIGH dv/dt CAPABILITY
s 100% AVALANCHE TESTED
s VERY LOW INTRINSIC CAPACITANCES
s GATE CHARGE MINIMIZED
DESCRIPTION
Using the latest high voltage MESH OVERLAY
process, STMicroelectronics has designed an
advanced family of power MOSFETs with
outstanding performances. The new patent
pending strip layout coupled with the Company’s
proprietary edge termination structure, gives the
lowest RDS(on) per area, exceptional avalanche
and dv/dt capabilities and unrivalled gate charge
and switching characteristics.
3
2
1
3
2
1
TO-220
TO-220FP
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
s HIGH CURRENT, HIGH SPEED SWITCHING
s SWITCH MODE POWER SUPPLIES (SMPS)
s DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
ABSOLUTE MAXIMUM RATINGS
Sy mb o l
Parameter
VDS Drain-source Volt age (VGS = 0)
V DGR
VGS
ID
ID
Drain- gate Voltage (RGS = 20 k)
Gate-source Voltage
Drain Current (continuous) at Tc = 25 oC
Drain Current (continuous) at Tc = 100 oC
IDM() Drain Current (pulsed)
Ptot Total Dissipation at Tc = 25 oC
Derating Factor
dv/dt(1) Peak Diode Recovery voltage slope
VISO Insulat ion Withstand Voltage (DC)
Tstg Storage Temperature
Tj Max. Operating Junction Temperature
() Pulse width limited by safe operating area
(*) Limited only by maximum temperature allowed
November 1999
Value
STP10NC50 STP10NC50FP
500
500
± 30
10 10(*)
6.3 6.3(*)
40 40
135 40
1.08
0.32
33
2000
-65 to 150
150
( 1) ISD 10 A, di/dt 100 A/µs, VDD V(BR)DSS, Tj TJMAX
Un it
V
V
V
A
A
A
W
W /o C
V/ns
V
oC
oC
1/7
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