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PDF PM25LV010 Data sheet ( Hoja de datos )
| Número de pieza | PM25LV010 | |
| Descripción | (PM25LV010 / 020 / 040) Serial Flash Memory | |
| Fabricantes | PMC | |
| Logotipo |  |
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( DataSheet : www.DataSheet4U.com )
PMC
Pm25LV010 / 020 / 040
1 Mbit / 2 Mbit / 4 Mbit 3.0 Volt-only,
Serial Flash Memory With 33 MHz SPI Bus Interface
FEATURES
Single Power Supply Operation
- Low voltage range: 2.7 V - 3.6 V
• Memory Organization
- Pm25LV010: 128K x 8 (1 Mbit)
- Pm25LV020: 256K x 8 (2 Mbit)
- Pm25LV040: 512K x 8 (4 Mbit)
Cost Effective Sector/Block Architecture
- 1Mb : Uniform 4Kbyte sectors / Four uniform
32Kbyte blocks
- 2Mb : Uniform 4Kbyte sectors / Four uniform
64Kbyte blocks
- 4Mb : Uniform 4Kbyte sectors / Eight uniform
64Kbyte blocks
- Bottom sector is configurable as one 4Kbyte sector
or four 1Kbyte sectors
Serial Peripheral Interface (SPI) Compatible
- Supports SPI Modes 0 (0,0) and 3 (1,1)
- Maximum 33 MHz clock rate for fast read
- Maximum 33 MHz clock rate for read
Page Program (up to 256 Bytes) Operation
- Typical 2 ms per page program
Sector, Block or Chip Erase Operation
- Typical 40 ms sector, block or chip erase
Software Write Protection
- The Block Protect (BP2, BP1, BP0) bits allow partial
or entire memory to be configured as read-only
Hardware Write Protection
- Protect and unprotect the device from write operation
by Write Protect (WP#) Pin
Low Power Consumption
- Typical 10 mA active read current
- Typical 15 mA program/erase current
High Product Endurance
- Guarantee 100,000 program/erase cycles per single
sector
- Minimum 20 years data retention
Industrial Standard Pin-out and Package
- 8-pin 150mil SOIC
- 8-pin 208mil SOIC for Pm25LV040
- 8-contact WSON
- Optional lead-free (Pb-free) package
GENERAL DESCRIPTION
The Pm25LV010/020/040 are 1 Mbit/2 Mbit/4 Mbit 3.0 Volt-only Serial Peripheral Interface (SPI) Flash memories.
The devices are designed to support 33 MHz fastest clock rate in the industry in normal read mode, 33 MHz in fast
read mode and the bottom 4 Kbyte sector into four smaller 1 Kbyte sectors features. The devices use a single low
voltage, ranging from 2.7 Volt to 3.6 Volt, power supply to perform read, erase and program operations. The devices
can be programmed in standard EPROM programmers as well. The Pm25LV010-33 is backward compatible to their
predecessors Pm25LV010-25.
The Pm25LV010/020/040 are accessed through a 4-wire SPI Interface consists of Serial Data Input (Sl), Serial
Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. The devices support page program mode, 1 to
256 bytes data can be programmed into the memory in one program operation. The memory of Pm25LV010 is
divided into uniform 4 Kbyte sectors or uniform 32 Kbyte blocks (sector group - consists of eight adjacent sectors)
for data or code storage. The memory of Pm25LV020/040 are divided into uniform 4 Kbyte sectors or uniform 64
Kbyte blocks (sector group - consists of sixteen adjacent sectors). The devices have an innovative feature to
configure the bottom 4 Kbyte sector into four smaller 1 Kbyte sectors for eliminating additional serial EEPROM
needed for storing data. This is a further cost reduction for overall system.
The Pm25LV010/020/040 are manufactured on PMC’s advanced nonvolatile CMOS technology, pFLASH™. The
devices are offered in 8-pin SOIC and 8-contact WSON packages with operation frequency up to 33 MHz in fast read
and 33 MHz in normal read mode.
Programmable Microelectronics Corp.
www.DataSheet4U.com
1
Issue Date: July, 2005, Rev: 1.2
www.DataSheet4U.com
1 page  
PMC
Pm25LV010/020/040
SPI MODES DESCRIPTION
Multiple Pm25LV010/020/040 devices can be serially
connected onto the SPI serial bus controlled by a SPI
Master i.e. microcontroller as shown in Figure 1. The
devices support either of the two SPI modes:
Mode 0 (0, 0)
Mode 3 (1, 1)
The difference between these two modes is the clock
polarity when the SPI master is in Stand-by mode: the
serial clock remains at “0” (SCK = 0) for Mode 0 and the
clock remains at “1” (SCK = 1) for Mode 1. Please refer
to Figure 2. For both modes, the input data is latched on
the rising edge of Serial Clock (SCK), and the output
data is available from the falling edge of SCK.
Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices)
SPI Interface with
(0, 0) or (1, 1)
SDO
SDI
SCK
SCK SO SI
SCK SO SI
SCK SO SI
SPI Master
(i.e. Microcontroller)
CS3 CS2 CS1
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CE# WP# HOLD# CE# WP# HOLD# CE# WP# HOLD#
Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven, High or Low as appropriate.
Figure 2. SPI Modes Supported
Mode 0 (0, 0) SCK
Mode 3 (1, 1) SCK
SI MSB
SO
MSB
Programmable Microelectronics Corp.
5
Issue Date: July, 2005, Rev: 1.2
5 Page 
PMC
Pm25LV010/020/040
DEVICE OPERATION (CONTINUED)
READ PRODUCT IDENTIFICATION OPERATION
Table 9. Product Identification
The Read Product Identification (RDID) instruction al-
lows the user to read the manufacturer and product ID of
the devices. Refer to Table 9 Product Identification for
PMC manufacturer ID and device ID. The RDID instruc-
tion code is followed by three dummy bytes, each bit
being latched-in on SI during the rising edge of SCK.
Then the first manufacturer ID (9Dh) is shifted out on SO
with the MSB first, followed by the device ID and the
second manufacturer ID (7Fh), each bit been shifted out
during the falling edge of SCK. If the CE# stays low after
the last bit of second manufacturer ID is shifted out, the
manufacturer ID and device ID will be looping until the
pulled high of CE# signal.
Product Identification
Manufacturer ID
First Byte
Second Byte
Device ID:
Pm25LV010
Pm25LV020
Pm25LV040
Data
9Dh
7Fh
7Ch
7Dh
7Eh
Figure 3. Read Product Identification Sequence
CE#
SCK
SI
01
78 9
31
INSTRUCTION 3 Dummy Bytes
1010 1011b
38 39
46 47
54
HIGH IMPEDANCE
SO
Manufacture ID1
Device ID
Manufacture ID2
Programmable Microelectronics Corp.
11
Issue Date: July, 2005, Rev: 1.2
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PM25LV010.PDF ] | |
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