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PDF M81C55 Data sheet ( Hoja de datos )
| Número de pieza | M81C55 | |
| Descripción | MSM81C55 | |
| Fabricantes | OKI | |
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¡ Semiconductor¡ Semiconductor
MThSiMs v8e1rCsi5o5n-:5JRaSn/. G19S9/8JS
Previous version: Aug. 1996
MSM81C55-5RS/GS/JS
2048-Bit CMOS STATIC RAM WITH I/O PORTS AND TIMER
GENERAL DESCRIPTION
The MSM81C55-5 has a 2k-bit static RAM (256 bytes) with parallel I/O ports and a timer. It uses
silicon gate CMOS technology and consumes a standby current of 100 micro ampere, maximum,
while the chip is not selected. Featureing a maximum access time of 400 ns, the MSM81C55-5
can be used in an MSM80C85AH system without using wait states. The parallel I/O consists
of two 8-bit ports and one 6-bit port (both general purpose).
The MSM81C55-5 also contains a 14-bit programmable counter/timer which may be used for
sequence-wave generation or terminal count-pulsing.
FEATURES
• High speed and low power achieved with silicon gate CMOS technology
• 256 words x 8bits RAM
• Single power supply, 3 to 6 V
• Completely static operation
• On-chip address latch
• 8-bit programmable I/O ports (portDAataanSdheBe)t4U.com
• TTL Compatible
• RAM data hold characteristic at 2 V
• 6-bit programmable I/O port (port C)
• 14-bit programmable binary counter/timer
• Multiplexed address/data bus
• Direct interface with MSM80C85AH
• 40-pin Plastic DIP (DIP40-P-600-2.54): (Product name: MSM81C55-5RS)
• 44-pin Plastic QFJ (QFJ44-P-S650-1.27): (Product name: MSM81C55-5JS)
• 44-pin Plastic QFP (QFP44-P-910-0.80-2K): (Product name: MSM81C55-5GS-2K)
DataShee
FUNCTIONAL BLOCK DIAGRAM
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IO/M
AD0 - 7
CE
ALE
RD
WR
RESET
256 ¥ 8
Static
RAM
Timer
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TIMER IN
TIMER OUT
Port A
A 8 PA0 - 7
Port B
B 8 PB0 - 7
Port C
C 6 PC0 - 5
VCC (+5 V)
GNDDa(t0aVS)heet4U.com
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¡ Semiconductor
TIMING DIAGRAM
Read Cycle
CE
IO/M
AD0 - 7
ALE
RD
et4U.com
MSM81C55-5RS/GS/JS
tAD
Address
tAL tLA
tLL tRDE
tLC
Data Valid
tRD
tCC
tRDF
tCL
tRV
DataShee
Write Cycle
CE
IO/M
AD0 - 7
ALE
WR
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Address
tAL tLA
tLL tLC
Data Valid
tDW tCL
tWD
tCC tRV
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¡ Semiconductor
MSM81C55-5RS/GS/JS
(1) Programming the Command/Status (C/S) Register
The contents of the command register can be written during an I/O cycle by addressing it
with an I/O address of xxxxx000. Bit assignments for the register are shown below:
et4U.com
7654321
TM2 TM1 IEB IEA PC2 PC1 PB
0
PA
Definition of PA0 - 7
Definition of PB0 - 7
Definition of PC0 - 5
0= Input
1= Output
00=ALT1
11=ALT2
01=ALT3
10=ALT4
See the port
control
assignment
table.
Port A Interrupt Enable 1 = Enabled
Port B Interrupt Enable 0 = Disabled
Timer Command
00 = NOP : Does not affect counter operations.
01 = STOP : Stops the timer if it is runnning.
NOP if the timer is not runnning.
10 = STOP AFTER TC : Stops the timer when it reaches TC.
NOP if the timer is not running.
11 = START : If the timer is not running, loads the mode and
DataSthheeecot4uUnt.lceongmth, and immediately starts timer operation.
If the timer is running, loads a new mode and the count
length, and starts timer operation immediately after
TC is reached.
DataShee
Port Control Assignment Table
Pin
ALT1
ALT2
ALT3
ALT4
PC0
Input port
Output port
A INTR
A INTR
PC1
Input port
Output port
A BF
A BF
PC2
Input port
Output port
A STB
A STB
PC3
Input port
Output port
Output port
B INTR
PC4
Input port
Output port
Output port
B BF
PC5
Input port
Output port
Output port
B STB
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11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet M81C55.PDF ] | |
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