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PDF P1014AP Data sheet ( Hoja de datos )

Número de pieza P1014AP
Descripción NCP1014AP
Fabricantes ON Semiconductor 
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1. P1014AP






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NCP1010, NCP1011,
NCP1012, NCP1013,
NCP1014
Self−Supplied Monolithic
Switcher for Low Standby−
Power Offline SMPS
http://onsemi.com
The NCP101X series integrates a fixed−frequency current−mode
controller and a 700 V MOSFET. Housed in a PDIP−7,
MARKING DIAGRAMS
PDIP−7 Gull Wing, or SOT−223 package, the NCP101X offers
everything needed to build a rugged and low−cost power supply,
including soft−start, frequency jittering, short−circuit protection,
skip−cycle, a maximum peak current setpoint and a Dynamic
Self−Supply (no need for an auxiliary winding).
8
PDIP−7
CASE 626A
AP SUFFIX
P101xAPyy
AWL
YYWW
Unlike other monolithic solutions, the NCP101X is quiet by nature:
during nominal load operation, the part switches at one of the available
1
1
frequencies (65 − 100 − 130 kHz). When the current setpoint falls
below a given value, e.g. the output power demand diminishes, the IC
automatically enters the so−called skip−cycle mode and provides
excellent efficiency at light loads. Because this occurs at typically 1/4
of the maximum peak value, no acoustic noise takes place. As a result,
PDIP−7
(Gull Wing)
101xAPLyy
CASE 626AA
AWL
1 APL SUFFIX YYWW
1
standby power is reduced to the minimum without acoustic noise
generation.
4
Short−circuit detection takes place when the feedback signal fades
away, e.g. in true short−circuit conditions or in broken Optocoupler
cases. External disabling is easily done either simply by pulling the
4 SOT−223
CASE 318E
1 ST SUFFIX
101xy
ALYW
feedback pin down or latching it to ground through an inexpensive
SCR for complete latched−off. Finally soft−start and frequency
1
jittering further ease the designer task to quickly develop low−cost and x = Current Limit (0, 1, 2, 3, 4)
robust offline power supplies.
yy = 06 (65 kHz), 10 (100 kHz), 13 (130 kHz)
For improved standby performance, the connection of an auxiliary
winding stops the DSS operation and helps to consume less than
100 mW at high line. In this mode, a built−in latched overvoltage
protection prevents from lethal voltage runaways in case the
y
A
WL, L
YY, Y
= Oscillator Frequency
A (65 kHz), B (100 kHz), C (130 kHz)
= Assembly Location
= Wafer Lot
= Year
Optocoupler would brake. These devices are available in economical
WW, W = Work Week
8−pin dual−in−line and 4−pin SOT−223 packages.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
Features
dimensions section on page 22 of this data sheet.
Built−in 700 V MOSFET with Typical RDSon of 11 W
and 22 W
Auto−Recovery Internal Output Short−Circuit
Protection
Large Creepage Distance Between High−Voltage Pins
Below 100 mW Standby Power if Auxiliary Winding
Current−Mode Fixed Frequency Operation:
65 kHz – 100 kHz − 130 kHz
is Used
Internal Temperature Shutdown
Skip−Cycle Operation at Low Peak Currents Only:
Direct Optocoupler Connection
No Acoustic Noise!
Dynamic Self−Supply, No Need for an Auxiliary
Winding
SPICE Models Available for TRANsient Analysis
Pb−Free Packages are Available*
Internal 1.0 ms Soft−Start
Latched Overvoltage Protection with Auxiliary
Winding Operation
Typical Applications
Low Power AC/DC Adapters for Chargers
Auxiliary Power Supplies (USB, Appliances,
Frequency Jittering for Better EMI Signature
TVs, etc.)
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2004
September, 2004 − Rev. 10
1
Publication Order Number:
NCP1010/D

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P1014AP pdf
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NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C,
VCC = 8.0 V unless otherwise noted.)
Rating
Pin Symbol
Min
Typ
Max
Unit
SUPPLY SECTION AND VCC MANAGEMENT
VCC Increasing Level at which the Current Source Turns−off
VCC Decreasing Level at which the Current Source Turns−on
VCC Decreasing Level at which the Latch−off Phase Ends
VCC Decreasing Level at which the Internal Latch is Released
Internal IC Consumption, MOSFET Switching at 65 kHz
Internal IC Consumption, MOSFET Switching at 100 kHz
1 VCCOFF
1 VCCON
1 VCClatch
1 VCCreset
1 ICC1
1 ICC1
7.9
6.9
4.4
8.5 9.1 V
7.5 8.1 V
4.7 5.1 V
3.0 − V
0.92 1.1 mA
(Note 2)
0.95 1.15 mA
(Note 2)
Internal IC Consumption, MOSFET Switching at 130 kHz
Internal IC Consumption, Latch−off Phase, VCC = 6.0 V
Active Zener Voltage Positive Offset to VCCOFF
Latch−off Current
NCP1012/13/14
NCP1010/11
1 ICC1
1 ICC2
1 Vclamp 140
1 ILatch
6.3
5.8
0.98 1.2 mA
(Note 2)
290 − mA
200 300 mV
mA
7.4 9.2
7.3 9.0
POWER SWITCH CIRCUIT
Power Switch Circuit On−state Resistance
NCP1012/13/14 (Id = 50 mA)
TJ = 25°C
TJ = 125°C
NCP1010/11 (Id = 50 mA)
TJ = 25°C
TJ = 125°C
Power Switch Circuit and Startup Breakdown Voltage
(ID(off) = 120 mA, TJ = 25°C)
Power Switch and Startup Breakdown Voltage Off−state
Leakage Current
TJ = 25°C (Vds = 700 V)
TJ = 125°C (Vds = 700 V)
5 RDSon
5 BVdss 700
IDS(OFF)
5
5
11
19
22
38
50
30
W
16
24
35
50
−V
mA
Switching Characteristics
(RL = 50 W, Vds Set for Idrain = 0.7 x Ilim)
Turn−on Time (90%−10%)
Turn−off Time (10%−90%)
ns
5 ton − 20 −
5 toff − 10 −
INTERNAL STARTUP CURRENT SOURCE
High−voltage Current Source, VCC = 8.0 V
NCP1012/13/14
NCP1010/11
High−voltage Current Source, VCC = 0
CURRENT COMPARATOR TJ = 25°C (Note 2)
Maximum Internal Current Setpoint, NCP1010 (Note 3)
Maximum Internal Current Setpoint, NCP1011 (Note 3)
Maximum Internal Current Setpoint, NCP1012 (Note 3)
Maximum Internal Current Setpoint, NCP1013 (Note 3)
Maximum Internal Current Setpoint, NCP1014 (Note 3)
Default Internal Current Setpoint for Skip−Cycle Operation,
Percentage of Max Ip
Propagation Delay from Current Detection to Drain OFF State
Leading Edge Blanking Duration
2. See characterization curves for temperature evolution.
3. Adjust di/dt to reach Ipeak in 3.2 msec.
1 IC1
mA
5.0 8.0 10
5.0 8.5 10.3
1 IC2 − 10 − mA
5 Ipeak (22)
90
100 110 mA
5 Ipeak (22) 225 250 275 mA
5 Ipeak (11) 225 250 275 mA
5 Ipeak (11) 315 350 385 mA
5 Ipeak (11) 405 450 495 mA
− ILskip
25
−%
− TDEL − 125 − ns
− TLEB − 250 − ns
http://onsemi.com
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NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
Tstart
Tsw
1 V Ripple
TLatch
Latch−off
Level
Figure 16. NCP101X Facing a Fault Condition (Vin = 150 Vdc)
The rising slope from the latch−off level up to 8.5 V
is
expressed
by:
Tstart
+
DV1 ·
IC1
C
.
The
time
during
which
the
IC
actually
pulses
is
given
by
tsw
+
DV2 · C
ICC1
.
Finally, the latch−off time can be derived
using
the
same
formula
topology:
TLatch
+
DV3 · C
ICC2
.
From these three definitions, the burst duty−cycle
can
be
computed:
dc
+
Tsw
Tstart ) Tsw ) TLatch
(eq. 2)
.
ǒ Ǔdc +
DV2
ICC1 ·
DV2
ICC1
)
DV1
IC1
)
DV3
ICC2
(eq. 3) .
Feeding
the
equation with values extracted from the parameter section
gives a typical duty−cycle of 13%, precluding any lethal
thermal runaway while in a fault condition.
DSS Internal Dissipation
The Dynamic Self−Supplied pulls energy out from the
drain pin. In Flyback−based converters, this drain level can
easily go above 600 V peak and thus increase the stress on the
DSS startup source. However, the drain voltage evolves with
time and its period is small compared to that of the DSS. As
a result, the averaged dissipation, excluding capacitive losses,
can be derived by: PDSS + ICC1 · t Vds(t) u . (eq. 4) .
Figure 17 portrays a typical drain−ground waveshape where
leakage effects have been removed.
Vds(t)
Vr
Vin
toff
dt
ton
Tsw
t
Figure 17. A typical drain−ground waveshape
where leakage effects are not accounted for.
By looking at Figure 17, the average result can easily be
derived by additive square area calculation:
t
Vds(t) u+ Vin ·
(1 * d) ) Vr
·
toff
Tsw
By developing Equation 5, we obtain:
(eq. 5)
t
Vds(t)
u+ Vin * Vin
·
ton
Tsw
)
Vr
·
toff
Tsw
(eq. 6)
toff
can
be
expressed
by:
toff
+
Ip
·
Lp
Vr
(eq. 7)
where ton
can
be
evaluated
by:
ton
+
Ip
·
Lp
Vin
(eq. 8)
.
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