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P7NB60FP fiches techniques PDF

ST Microelectronics - STP7NB60FP

Numéro de référence P7NB60FP
Description STP7NB60FP
Fabricant ST Microelectronics 
Logo ST Microelectronics 





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P7NB60FP fiche technique
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STP7NB60
STP7NB60FP
N - CHANNEL ENHANCEMENT MODE
PowerMESHMOSFET
TYPE
V DSS
RDS(on)
ID
STP7NB60
S TP7NB 60F P
600 V
600 V
< 1.2
< 1.2
7.2 A
4.1 A
s TYPICAL RDS(on) = 1.0
s EXTREMELY HIGH dv/dt CAPABILITY
s 100% AVALANCHE TESTED
s VERY LOW INTRINSIC CAPACITANCES
s GATE CHARGE MINIMIZED
DESCRIPTION
Using the latest high voltage MESH OVERLAY
process, SGS-Thomson has designed an
advanced family of power MOSFETs with
outstanding performances. The new patent
pending strip layout coupled with the Company’s
proprietary edge termination structure, gives the
lowest RDS(on) per area, exceptional avalanche
and dv/dt capabilities and unrivalled gate charge
and switching characteristics.
APPLICATIONS
s HIGH CURRENT, HIGH SPEED SWITCHING
s SWITCH MODE POWER SUPPLIES (SMPS)
s DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
3
2
1
TO-220
3
2
1
TO-220FP
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
S ym b o l
Parameter
VDS Drain-source Voltage (VGS = 0)
VDGR
VGS
ID
ID
IDM ( )
Ptot
Drain- gate Volt age (RGS = 20 k)
Gate-source Voltage
Drain Current (continuous) at Tc = 25 oC
Drain Current (continuous) at Tc = 100 oC
Drain Current (pulsed)
Tot al Dissipation at Tc = 25 o C
Derating Factor
dv/dt(1) Peak Diode Recovery voltage slope
VISO Insulation W it hstand Voltage (DC)
Tstg Storage Temperature
Tj Max. O perating Junction Temperature
() Pulse width limited by safe operating area
March 1998
Value
ST P7NB60 STP7NB60FP
600
600
± 30
7.2 4.1
4.5 2.6
28.8
28.8
125 40
1.0 0.32
4.5 4.5
2000
-65 to 150
150
(1) ISD 7A, di/dt 200 A/µs, VDD V(BR)DSS, Tj TJMAX
Uni t
V
V
V
A
A
A
W
W/oC
V/ ns
V
oC
oC
1/9

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