PDF ADF4252 Data sheet ( Hoja de datos )

Número de pieza	ADF4252
Descripción	Dual Fractional-N/Integer-N Frequency Synthesizer
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet Dual Fractional-N/Integer-N Frequency Synthesizer ADF4252 FEATURES GENERAL DESCRIPTION 3.0 GHz fractional-N/1.2 GHz integer-N 2.7 V to 3.3 V power supply Separate VP allows extended tuning voltage to 5 V Programmable dual modulus prescaler RF: 4/5, 8/9 IF: 8/9, 16/17, 32/33, 64/65 Programmable charge pump currents 3-wire serial interface Digital lock detect Power-down mode Programmable modulus on fractional-N synthesizer Trade off noise vs. spurious performance APPLICATIONS Base stations for mobile radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs Communications test equipment CATV equipment The ADF4252 is a dual fractional-N/integer-N frequency synthesizer that can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters. Both the RF and IF synthesizers consist of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. The RF synthesizer has a Σ-Δ-based fractional interpolator that allows programmable fractional-N division. The IF synthesizer has programmable integer-N counters. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). Control of all the on-chip registers is via a simple 3-wire interface. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use. FUNCTIONAL BLOCK DIAGRAM VDD1 VDD2 VDD3 DVDD VP1 VP2 RSET ADF4252 REFERENCE REFIN 2 DOUBLER 4-BIT R COUNTER PHASE FREQUENCY DETECTOR CHARGE PUMP CPRF REFOUT MUXOUT OUTPUT MUX LOCK DETECT CLK DATA LE 24-BIT DATA REGISTER FRACTIONAL-N RF DIVIDER INTEGER-N IF DIVIDER RFINA RFINB IFINB IFINA 2 DOUBLER 15-BIT R COUNTER PHASE FREQUENCY DETECTOR CHARGE PUMP CPIF Figure 1. AGND1 AGND2 DGND CPGND1 CPGND2 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2003–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page ADF4252 Data Sheet SPECIFICATIONS VDD1 = VDD2 = VDD3 = DVDD = 3 V ± 10%, DVDD < VP1, VP2 < 5.5 V, GND = 0 V, RSET = 2.7 kΩ, dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter1 RF CHARACTERISTICS RF Input Frequency (RFINA, RFINB)2 RF Input Sensitivity RF Input Frequency (RFINA, RFINB)2 RF Phase Detector Frequency Allowable Prescaler Output Frequency IF CHARACTERISTICS IF Input Frequency (IFINA, IFINB)2 IF Input Sensitivity IF Phase Detector Frequency Allowable Prescaler Output Frequency REFERENCE CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity REFIN Input Current REFIN Input Capacitance CHARGE PUMP RF ICP Sink/Source High Value Low Value IF ICP Sink/Source High Value Low Value ICP Three-State Leakage Current RF Sink and Source Current Matching RSET Range IF Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage Min Typ 0.25 −10 0.1 50 −10 0.5 4.375 625 5 625 1 2 1.5 2.7 2 2 2 1.35 VDD − 0.4 Max 3.0 0 3.0 30 375 1200 0 55 150 250 VDD1 ±100 10 5.6 0.6 ±1 10 0.4 Unit GHz dBm GHz MHz MHz MHz dBm MHz MHz MHz V p-p µA pF mA µA mA µA nA % kΩ % % % V V µA pF V V Test Conditions/Comments Input level = −8 dBm minimum, 0 dBm maximum Guaranteed by design Guaranteed by design For f < 10 MHz, use dc-coupled square wave (0 V to VDD) AC-coupled; when dc-coupled, use 0 V to VDD max (CMOS-compatible) See Figure 37 See Figure 41 0.5 V < VCP < VP − 0.5 See Figure 37 0.5 V < VCP < VP − 0.5 VCP = VP/2 IOH = 0.2 mA IOL = 0.2 mA Rev. C \| Page 4 of 30 5 Page ADF4252 Data Sheet For Figure 16 to Figure 21, across all fractional channel steps from f = 0/130 to f = 129/130, RFOUT = 1.45 GHz, INT = 55, REFIN = 26 MHz, and loop bandwidth = 40 kHz. Plots attained using the EVAL-ADF4252EB2 evaluation board. –70 –20 –75 –30 –80 –40 –85 –90 LOWEST SPUR MODE –95 –50 –60 –70 LOWEST NOISE MODE –100 –105 –110 LOW NOISE AND SPUR MODE LOWEST NOISE MODE –80 –90 –100 –115 –120 1.430 1.435 1.440 1.445 1.450 FREQUENCY (GHz) 1.455 Figure 16. In-Band Phase Noise vs. Frequency 1.460 –110 LOWEST SPUR MODE –120 1.430 1.435 1.440 1.445 1.450 FREQUENCY (GHz) 1.455 Figure 19. 400 kHz Spur vs. Frequency 1.460 –10 –20 –30 –40 LOWEST NOISE MODE –50 –60 –70 –80 –90 –100 LOWEST SPUR MODE –110 1.430 1.435 1.440 1.445 1.450 FREQUENCY (GHz) 1.455 Figure 17. 100 kHz Spur vs. Frequency 1.460 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 1.430 LOWEST NOISE MODE LOWEST SPUR MODE 1.435 1.440 1.445 1.450 FREQUENCY (GHz) 1.455 Figure 20. 600 kHz Spur vs. Frequency 1.460 –20 –30 –40 –50 –60 LOWEST NOISE MODE –70 –80 –90 –100 –110 LOWEST SPUR MODE –120 1.430 1.435 1.440 1.445 1.450 FREQUENCY (GHz) 1.455 1.460 Figure 18. 200 kHz Spur vs. Frequency –20 –30 –40 –50 –60 –70 –80 –90 –100 LOWEST NOISE MODE –110 –120 1.430 LOWEST SPUR MODE 1.435 1.440 1.445 1.450 FREQUENCY (GHz) 1.455 1.460 Figure 21. 3 MHz Spur vs. Frequency Rev. C \| Page 10 of 30 11 Page

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