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PDF ATF1502SL Data sheet ( Hoja de datos )
| Número de pieza | ATF1502SL | |
| Descripción | (ATF1502SE - ATF1516SE) Family Datasheet | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• 2nd Generation EE PROM-based Complex Programmable Logic Devices
– VCCIO of 5.0V or 3.3V with 3.3V Operation being 5V Tolerant
– 32 - 256 Macrocells with Enhanced Features
– Pin-compatible with Industry Standard Devices
– Speeds to 5 ns Maximum Pin-to-pin Delay
– Registered Operation to 250 MHz
• Enhanced Macrocells with Logic Doubling™ Features
– Bury Either Register or COM while Using the Other for Output
– Dual Independent Feedback Allows Multiple Latch Functions per Macrocell
– 5 Product Terms per Macrocell, expandable to 40 per Macrocell with Cascade
Logic, Plus 15 more with Foldback Logic
– D/T/Latch Configurable Flip-flops plus Transparent Latches
– Global and/or per Macrocell Register Control Signals
– Global and/or per Macrocell Output Enable
– Programmable Output Slew Rate per Macrocell
– Programmable Output Open Collector Option per Macrocell
– Fast Registered Input from Product Term
• Enhanced Connectivity
– Single Level Switch Matrix for Maximum Routing Options
– Up to 40 Inputs per Logic Block
• Advanced Power Management Features
– ITD (Input Transition Detection) Available Individually on Global Clocks, Inputs and
I/O for µA Level Standby Current for “L” Versions
– Pin-controlled 1 mA Standby Mode
– Reduced-power Option per Macrocell
– Automatic Power Down of Unused Macrocells
– Programmable Pin-keeper Inputs and I/Os
• Available in Commercial and Industrial Temperature Ranges
• Available in All Popular Packages Including PLCC, PQFP and TQFP
• EE PROM Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
• JTAG Boundary-scan Testing Port per IEEE 1149.1-1990 and 1149.1a-1993
– Pull-up Option on JTAG Pins TMS and TDI
• IEEE 1532 Compatibility for Fast In-System Programmability (ISP) via JTAG
• PCI-compliant
• Security Fuse Feature
ATF15xxSE
Family
Datasheet
ATF1502SE(L)
ATF1504SE(L)
ATF1508SE(L)
ATF1516SE(L)
Preliminary
DataSheet4 U .com
Rev. 2401D–PLD–09/02
1
1 page  
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ATF15xxSE Family
Figure 2. ATF15xxSE Family Macrocell with Enhanced Features In Red
SWITCH REGIONAL
MATRIX FOLDBACK
CASIN
OUTPUTS
BUS
LOGIC
FOLDBACK
80 16
40
1
PT1
PT2
PT3
GOE[0:5]
6
2
3
4
GOE [0:5]
SMWGAOTITRECIXH
5
Q
!Q
PT4
PT5
GCK[0:2]
I/O Pin
3
AP
D/T*/L
Q
CK/CK/LE
CE
AR
!Q
GCLEAR
I/O Pin
SLEW
RATE
OPEN
COLLECTOR
GLOBAL BUS
CASOUT
Reduced Power Option
* T flip-flop synthesised
Product Terms and
Select Mux
OR/XOR/
CASCADE Logic
Foldback Bus
Within each macrocell are five product terms. Each product term may receive as its inputs any
combination of the signals from the switch matrix or regional foldback bus. The product term
select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic
gates and control signals. The PTMUX programming is determined by the fitter software,
which selects the optimum macrocell configuration.
Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5-
input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can
be expanded to as many as 40 product terms with little additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic func-
tions. One input to the XOR comes from the OR sum term. The other XOR input can be a
product term or a fixed high- or low-level. For combinatorial outputs, the fixed level input
allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimiza-
tion of product terms. The XOR gate may be fed from the flip-flop output to emulate T- and JK-
type flip-flops, or fed to the buried feedback to synthesize an extra latch.
Each macrocell can also generate a foldback product term. This signal goes to the regional
bus and is available to the 16 macrocells in a given logic block. The foldback is an inverse
polarity of one of the macrocell’s product terms. Although Cascade Logic is the preferred
method for expanding the number of macrocell inputs to as many as 40, the 16 foldback terms
in each region can also generate additional fan-in sum terms with nominal additional delay.
2401D–PLD–09/02
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JTAG-BST
Overview
ATF15xxSE Family
The JTAG-BST (JTAG boundary-scan testing) is controlled by the Test Access Port (TAP)
controller. The boundary-scan technique involves the inclusion of a shift-register stage (con-
tained in a boundary-scan cell) adjacent to each component so that signals at component
boundaries can be controlled and observed using scan testing principles. Each input pin and
I/O pin has its own Boundary-scan Cell (BSC) in order to support boundary-scan testing. The
ATF15xxSE Family does not currently include a Test Reset (TRST) input pin because the TAP
controller is automatically reset at power-up. The ATF15xxSE Family implements six BST
instructions, and seven Atmel-defined In System Programming (ISP) instructions. All ATF15xx
Family BST and ISP instructions have a length of 10 bits.
JTAG BST Instructions
SAMPLE/PRELOAD
EXTEST
BYPASS
IDCODE
UESCODE
HIGHZ
7 ISP instructions
Description
Captures signals at the device pins for later examination,
or loads a data pattern prior to an EXTEST instruction.
Allows testing of off-chip circuitry and interconnections
by forcing a pattern on the output pins or capturing
signals from the input pins.
Places a single shift register stage between TDI and
TDO, allowing test BST data to pass through a particular
device in a chain of devices.
Places the 32-bit IDCODE register between TDI and
TDO, allowing the IDCODE data to be shifted out of
TDO.
Places the 16-bit user electronic signature register
between TDI and TDO, allowing the UESCODE data to
be shifted out of TDO.
Places the BYPASS register between TDI and TDO in a
high impedance mode, protecting the device from
damage from externally applied test signals.
These seven instructions allow in-system programming
via the four JTAG pins.
The ATF15xxSE Family BST implementation complies with the Boundary-scan Definition Lan-
guage (BSDL) described in the JTAG specification (IEEE Standard 1149.1). Any third-party
tool that supports the BSDL format can be used to perform BST on the ATF15xxSE Family.
The ATF15xxSE Family also has the option of using four JTAG-standard I/O pins for in-system
programming (ISP). The ATF15xxSE Family is programmable through the four JTAG pins
using programming-compatible with the IEEE JTAG Standard 1149.1. Programming is per-
formed by using 5V TTL-level programming signals from the JTAG ISP interface. The JTAG
feature is a programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG
control pins are available as I/O pins. Refer to Atmel Application Note “Designing for In-Sys-
tem Programmability with Atmel CPLDs for more details.
2401D–PLD–09/02
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| PDF Descargar | [ Datasheet ATF1502SL.PDF ] | |
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