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PDF T224162B Data sheet ( Hoja de datos )
| Número de pieza | T224162B | |
| Descripción | 256K x 16 DYNAMIC RAM EDO PAGE MODE | |
| Fabricantes | Taiwan Memory Technology | |
| Logotipo |  |
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tm TE
CH
DRAM
T224162B
256K x 16 DYNAMIC
RAM
EDO PAGE MODE
FEATURES
• Industry-standard x 16 pinouts and timing
functions.
• Single 5V (±10%) power supply.
• All device pins are TTL- compatible.
• 512-cycle refresh in 8ms.
• Refresh modes: RAS only, CAS BEFORE
RAS (CBR) and HIDDEN.
• Extended data-out (EDO) PAGE MODE
access cycle.
• BYTE WRITE and BYTE READ access
cycles.
OPTION
TIMING
22n s
25ns
28n s
35ns
45n s
50ns
PACKAGE
SOJ
TSOP(II)
EDO
125 MHz
100 MHz
100 MHz
83 MHz
60 MHz
50 MHz
MARKING
J
S
MARKING
-22
-25
-28
-35
-45
-50
GENERAL DESCRIPTION
The T224162B is a randomly accessed solid state
memory containing 4,194,304 bits organized in a x16
configuration. The T224162B has both BYTE
WRITE and WORD WRITE access cycles via two
CAS pins. It offers Fast Page mode with Extended
Data Output.
The T224162B CAS function and timing are
determined by the first CAS to transition low and
by the last to transition back high. Use only one of
the two CAS and leave the other staying high during
WRITE will result in a BYTE WRITE. CASL
transiting low in a WRITE cycle will write data into
the lower byte (IO1~IO8), and CASH transiting low
will write data into the upper byte (IO9~16).
PIN ASSIGNMENT ( Top View )
Vcc 1
I/01 2
I/02 3
I/03 4
I/04 5
Vcc 6
I/05 7
I/06 8
I/07 9
I/08 10
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
11
12
13
14
15
16
17
18
19
20
TSOP(II)
40 Vss
39 I/016
38 I/015
37 I/014
36 I/013
35 Vss
34 I/012
33 I/011
32 I/010
31 I/09
30 NC
29 CASL
28 CASH
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 VSS
Vcc
I/01
I/02
I/03
I/04
Vcc
I/05
I/06
I/07
I/08
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SOJ
40 Vss
39 I/016
38 I/015
37 I/014
36 I/013
35 Vss
34 I/012
33 I/011
32 I/010
31 I/09
30 NC
29 CASL
28 CASH
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 VSS
Taiwan Memory Technology, Inc. reserves the right P. 1
to change products or specifications without notice.
Publication Date: AUG. 2000
Revision:L
DataSheet4 U .com
1 page  
www.DataSheet4U.com
tm TE
CH
T224162B
AC ELECTRICAL CHARACTERISTICS (continued)
AC CHARACTERISTICS SYM
PARAMETER
Row Address Setup Time tASR
Row Address Hold Time tRAH
RAS to Column Address
Delay Time
tRAD
-22 -25 -28
MIN MAX MIN MAX MIN MAX
000
555
8 11 8 12 8 13
-35 -45 - 50 UNIT Notes
MIN MAX MIN MAX MIN MAX
0 0 0 ns
5 5 5 ns
8
8 20 8 26 10 29 ns
Column Address Setup Time tASC 0 0 0 0 0 0 ns 18
Column Address Hold Time tCAH 4 4 4 4 6 7 ns 18
Column Address Hold Time
(Reference to RAS )
tAR 17
19
21
30
40
45
ns
Column Address to RAS
Lead Time
tRAL 11
12
13
15
19
23
ns
Read Command Setup Time tRCS 0 0 0 0 0 0 ns 15,18
ReadCommandHoldTime
9,15,
Referenceto CAS
tRCH 0 0 0 0 0 0 ns 19
ReadCommandHoldTime
9
Referenceto RAS
tRRH 0 0 0 0 0 0 ns
CAS to Output in Low-Z tCLZ 3 3 3 3 3 3 ns 20
Output Buffer Turn-off
10,17,
Delay From CAS or RAS tOFF1 3 3 3 3 15 3 15 3 15 ns 20
Output Buffer Turn-off to
17,28
OE
tOFF2
8
8
8
8
8
8 ns
Write Command Setup Time tWCS 0
0
0
0
0
0 ns 11,15,
18
Write Command Hold Time tWCH 4 4 4 4 6 7 ns 15,27
Write Command Hold Time
15
(Reference to RAS )
tWCR 19
19
21
30
46
51
ns
Write Command Pulse
Width
tWP 4
4
4
4
6
8 ns 15
Write Command to RAS
Lead Time
tRWL 6
6
6
7
15
9 10 ns
Write Command to CAS
Lead Time
tCW L 5
5
5
7
15,19
9 11 ns
Data-in Setup Time tDS 0 0 0 0 0 0 ns 12,20
Data-in Hold Time
tDH 4 4 4 4 6 7 ns 12,20
Data-in Hold Time
(Reference to RAS )
tDHR 19
19
21
30
40
45
ns
RAS to WE Delay Time tRWD 31 34 37 51 61 70 ns 11
AC ELECTRICAL CHARACTERISTICS (continued)
Taiwan Memory Technology, Inc. reserves the right P. 5
to change products or specifications without notice.
Publication Date:AUG. 2000
Revision:L
DataSheet4 U .com
5 Page 
www.DataSheet4U.com
tm TE
CH
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE
(Psuedo READ-MODIFY-WRITE)
T224162B
RA S
VVII
H
L
C AS
VVII
H
L
ADDR
VVII
H
L
WE
VVII
H
L
I/O
VVII
OH
OL
OE
VIH
VIL
t R A SC
tC R P
tCSH
tPC tPC
tR C D
t C A S tC P tC A S t C P
tR S H
tC A S
t R AD
tA S R t R A H
ROW
tAR
tA S C
tC A H
C O LU M N(A)
tRCS
tA SC tC A H
C O LUMN(B )
tRCH
tR A L
tA S C t C A H
C O L U MN (N )
tWC S
tWC H
tA A
tR A C
tCAC
OP EN
tOA C
t AC P
tA A
tC A C
tC O H
VA LID DA TA (A)
t WHZ
V A L ID
D A T A (B )
tDS t DH
VALID DATA
IN
tR P
tC P
RO W
R AS
V
V
IH
IL
CA SL ,C A SH
V
V
IH
IL
A DDR
V
V
IH
IL
I /O
V
V
OH
OL
RAS ONLY REFRESH CYCLE
(ADDR=A0-A8 ; OE , W E =DON‘T CARE)
tC R P
tA SR
tRAH
RO W
tR A S
tR C
tR P
t RP C
OP EN
ROW
DON'T CARE
UNDEFINE D
Taiwan Memory Technology, Inc. reserves the right P. 11
to change products or specifications without notice.
DataSheet4 U .com
Publication Date: AUG. 2000
Revision:L
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet T224162B.PDF ] | |
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