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PDF ATA6826 Data sheet ( Hoja de datos )
| Número de pieza | ATA6826 | |
| Descripción | Triple Half-bridge DMOS Output Driver with Serial Input Control | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Supply Voltage up to 40V
• RDSon Typically 0.8Ω at 25°C, Maximum 1.5Ω at 150°C
• Up to 1.0A Output Current
• Three Half-bridge Outputs Formed by Three High-side and Three Low-side Drivers
• Capable of Switching all Kinds of Loads Such as DC Motors, Bulbs, Resistors,
Capacitors and Inductors
• No Shoot-through Current
• Very Low Quiescent Current IS < 5 µA in Standby Mode versus Total Temperature
Range
• Outputs Short-circuit Protected
• Overtemperature Protection for Each Switch and Overtemperature Prewarning
• Undervoltage Protection
• Various Diagnostic Functions Such as Shorted Output, Open-load, Overtemperature
and Power-supply Fail Detection
• Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency
• SO14 Power Package
1. Description
The ATA6826 is a fully protected Triple Half-bridge designed in Smart Power SOI
Technology, used to control up to 3 different loads by a microcontroller in automotive
and industrial applications.
Each of the 3 high-side and 3 low-side drivers is capable of driving currents up to
1.0A. The drivers are internally connected to form 3 half-bridges and can be controlled
separately from a standard serial data interface. Therefore, all kinds of loads such as
bulbs, resistors, capacitors and inductors can be combined. The IC design especially
supports the application of H-bridges to drive DC motors.
Protection is guaranteed regarding short-circuit conditions, overtemperature and und-
ervoltage. Various diagnostic functions and a very low quiescent current in standby
mode opens a wide range of applications. Automotive qualification gives added value
and enhanced quality for exacting requirements of automotive applications.
Triple Half-
bridge DMOS
Output Driver
with Serial Input
Control
ATA6826
DataSheet4 U .com
4834C–BCD–06/06
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ATA6826
Table 3-2. Output Data Protocol
Output (Status)
Bit
Register
Function
0 TP Temperature prewarning: high = warning
1
Status LS1
High = output is on, low = output is off; not affected by SRR
2
Status HS1
High = output is on, low = output is off; not affected by SRR
3
Status LS2
Description see LS1
4
Status HS2
Description see HS1
5
Status LS3
Description see LS1
6
Status HS3
Description see HS1
7 n. u. Not used
8 n. u. Not used
9 n. u. Not used
10 n. u. Not used
11 n. u. Not used
12 n. u. Not used
Short circuit detected: set high when at least one high-side or low-side
13
SCD
switch is switched off by a short-circuit condition. Bits 1 to 6 can be used
to detect the shorted switch.
Open load detected: set high, when at least one active high-side or
14
OPL
low-side switch sinks/sources a current below the open load threshold
current.
15 PSF Power-supply fail: undervoltage at pin VS detected
After power-on reset, the input register has the following status:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7
(OCS)
xx H x x x x x x
Bit 6
(HS3)
L
Bit 5
(LS3)
L
Bit 4
(HS2)
L
Bit 3
(LS2)
L
Bit 2 Bit 1
(HS1) (LS1)
LL
Bit 0
(SRR)
L
The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during
normal operation.
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(OCS)
(HS3) (LS3) (HS2) (LS2) (HS1) (LS1) (SRR)
HH H H H L L L L L L L L LL L
HH H L L H H L L L L L L LL L
HH H L L L L H H L L L L LL L
4834C–BCD–06/06
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ATA6826
9. Serial Interface – Timing
No. Parameters
Test Conditions Pin Timing Chart No.(1) Symbol Min. Typ. Max. Unit Type*
8.1
DO enable after CS
falling edge
CDO = 100 pF
9
1
tENDO
200 ns
D
8.2
DO disable after CS
rising edge
CDO = 100 pF
9
2
tDISDO
200 ns
D
8.3 DO fall time
CDO = 100 pF
9
-
tDOf
100
8.4 DO rise time
CDO = 100 pF
9
-
tDOr
100
8.5 DO valid time
CDO = 100 pF
9
10
tDOVal
200
8.6 CS setup time
4
4
tCSSethl
225
8.7 CS setup time
4
8
tCSSetlh
225
8.8 CS high time
49
tCSh 500
8.9 CLK high time
65
tCLKh
225
8.10 CLK low time
66
tCLKl
225
8.11 CLK period time
6-
tCLKp
500
8.12 CLK setup time
6
7
tCLKSethl
225
8.13 CLK setup time
6
3
tCLKSetlh
225
8.14 DI setup time
5 11
tDIset
40
8.15 DI hold time
5 12
tDIHold
40
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. See Figure 9-1 on page 12 “Serial Interface Timing with Chart Numbers”
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D
D
D
D
D
D
D
D
D
D
D
D
D
4834C–BCD–06/06
DataSheet4 U .com
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11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ATA6826.PDF ] | |
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