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PDF AD9222 Data sheet ( Hoja de datos )
| Número de pieza | AD9222 | |
| Descripción | 40/50 MSPS Serial LVDS 1.8 V A/D Converter | |
| Fabricantes | Analog Devices | |
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Data Sheet
FEATURES
8 ADCs integrated into 1 package
114 mW ADC power per channel at 65 MSPS
SNR = 70 dB (to Nyquist)
ENOB = 11.3 bits
SFDR = 80 dBc
Excellent linearity: DNL = ±0.3 LSB (typical),
INL = ±0.4 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar IEEE 1596.3)
Data and frame clock outputs
325 MHz full-power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Full-chip and individual-channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Tape drives
Optical networking
Test equipment
GENERAL DESCRIPTION
The AD9222 is an octal, 12-bit, 40/50/65 MSPS analog-to-
digital converter (ADC) with an on-chip sample-and-hold
circuit designed for low cost, low power, small size, and ease of
use. The product operates at a conversion rate of up to 65 MSPS
and is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for
the appropriate LVDS serial data rate. A data clock output (DCO)
for capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-channel
power-down is supported and typically consumes less than
2 mW when all channels are disabled.
Octal, 12-Bit, 40/50/65 MSPS
Serial LVDS 1.8 V A/D Converter
AD9222
FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN
DRVDD DRGND
VIN + A
VIN – A
VIN + B
VIN – B
VIN + C
VIN – C
VIN + D
VIN – D
VIN + E
VIN – E
VIN + F
VIN – F
VIN + G
VIN – G
VIN + H
VIN – H
VREF
SENSE
REFT
REFB
AD9222
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
REF
SELECT
0.5V
SERIAL PORT
INTERFACE
12
SERIAL
LVDS
12
SERIAL
LVDS
12
SERIAL
LVDS
12
SERIAL
LVDS
12
SERIAL
LVDS
12
SERIAL
LVDS
12
SERIAL
LVDS
12
SERIAL
LVDS
DATA RATE
MULTIPLIER
D+A
D–A
D+B
D–B
D+C
D–C
D+D
D–D
D+E
D–E
D+F
D–F
D+G
D–G
D+H
D–H
FCO +
FCO –
DCO +
DCO –
RBIAS
AGND CSB
SDIO/ SCLK/
ODM DTP
Figure 1.
CLK+
CLK–
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user-
defined test patterns entered via the serial port interface (SPI).
The AD9222 is available in an RoHS compliant, 64-lead LFCSP. It is
specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Small Footprint. Eight ADCs are contained in a small,
space-saving package.
2. Low power of 114 mW/channel at 65 MSPS.
3. Ease of Use. A data clock output (DCO) is provided that
operates at frequencies of up to 390 MHz and supports
double data rate (DDR) operation.
4. User Flexibility. The SPI control offers a wide range of
flexible features to meet specific system requirements.
5. Pin-Compatible Family. This includes the AD9212 (10-bit)
and AD9252 (14-bit).
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved.
1 page  
AD9222
Data Sheet
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
WORST HARMONIC (Second or Third)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
WORST OTHER (Excluding Second or Third)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)—
AIN1 AND AIN2 = −7.0 dBFS
fIN1 = 15 MHz, fIN2 = 16 MHz
fIN1 = 70 MHz, fIN2 = 71 MHz
AD9222-40
AD9222-50
AD9222-65
Temp Min Typ Max Min Typ Max Min Typ Max Unit
Full 70.3
Full 69.5 70.3
Full 69.9
Full 68.8
70.4
69.5 70.3
70.0
69.0
70.3
68.5 70.0
69.8
69.5
dB
dB
dB
dB
Full 70.0
Full 68.7 70.0
Full 69.5
Full 68.0
70.0
68.5 70.0
69.8
68.5
69.5
66.8 69.4
69.3
69
dB
dB
dB
dB
Full 11.38
Full 11.25 11.38
Full 11.32
Full 11.14
11.25
11.4
11.38
11.33
11.17
11.4
11.1 11.34
11.30
11.25
Bits
Bits
Bits
Bits
Full
Full 73
Full
Full
85
85
80
76
85
73 84
83
77
83
70.5 80
80
75
dBc
dBc
dBc
dBc
Full −85
−85 −83 dBc
Full
−85 −74
−84 −73
−80 −70.5 dBc
Full −80
−83 −80 dBc
Full −76
−77 −75 dBc
Full −92
−92 −90 dBc
Full
−92 −80
−92 −80
−90 −80 dBc
Full −92
−92 −90 dBc
Full −90
−90 −85 dBc
25°C 80.0
25°C 77.0
80.0 80.0 dBc
77.0 75.0 dBc
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
Rev. F | Page 4 of 60
5 Page 
AD9222
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AVDD 1
VIN + G 2
VIN – G 3
AVDD 4
VIN – H 5
VIN + H 6
AVDD 7
AVDD 8
CLK– 9
CLK+ 10
AVDD 11
AVDD 12
DRGND 13
DRVDD 14
D – H 15
D + H 16
PIN 1
INDICATOR
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
AD9222
TOP VIEW
(Not to Scale)
48 AVDD
47 VIN + B
46 VIN – B
45 AVDD
44 VIN – A
43 VIN + A
42 AVDD
41 PDWN
40 CSB
39 SDIO/ODM
38 SCLK/DTP
37 AVDD
36 DRGND
35 DRVDD
34 D + A
33 D – A
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND
Figure 5. 64-Lead LFCSP Pin Configuration, Top View
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
0 AGND
1, 4, 7, 8, 11,
12, 37, 42, 45,
48, 51, 59, 62
AVDD
13, 36
DRGND
14, 35
DRVDD
2 VIN + G
3 VIN − G
5 VIN − H
6 VIN + H
9 CLK−
10 CLK+
15 D − H
16 D + H
17 D − G
18 D + G
19 D − F
20 D + F
21 D − E
22 D + E
23 DCO−
24 DCO+
25 FCO−
26 FCO+
27 D − D
28 D + D
29 D − C
30 D + C
31 D − B
32 D + B
Description
Analog Ground (Exposed Paddle)
1.8 V Analog Supply
Digital Output Driver Ground
1.8 V Digital Output Driver Supply
ADC G Analog Input True
ADC G Analog Input Complement
ADC H Analog Input Complement
ADC H Analog Input True
Input Clock Complement
Input Clock True
ADC H Digital Output Complement
ADC H Digital Output True
ADC G Digital Output Complement
ADC G Digital Output True
ADC F Digital Output Complement
ADC F Digital Output True
ADC E Digital Output Complement
ADC E Digital Output True
Data Clock Digital Output Complement
Data Clock Digital Output True
Frame Clock Digital Output Complement
Frame Clock Digital Output True
ADC D Digital Output Complement
ADC D Digital Output True
ADC C Digital Output Complement
ADC C Digital Output True
ADC B Digital Output Complement
ADC B Digital Output True
Rev. F | Page 10 of 60
Data Sheet
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9222.PDF ] | |
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