PDF AD9252 Data sheet ( Hoja de datos )

Número de pieza	AD9252
Descripción	1.8 V ADC
Fabricantes	Analog Devices
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Data Sheet FEATURES 8 analog-to-digital converters (ADCs) integrated into 1 package 93.5 mW ADC power per channel at 50 MSPS SNR = 73 dB (to Nyquist) ENOB = 12 bits SFDR = 84 dBc (to Nyquist) Excellent linearity DNL = ±0.4 LSB (typical); INL = ±1.5 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar to IEEE 1596.3) Data and frame clock outputs 325 MHz, full-power analog bandwidth 2 V p-p input voltage range 1.8 V supply operation Serial port control Full-chip and individual-channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Programmable clock and data alignment Programmable output resolution Standby mode APPLICATIONS Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment GENERAL DESCRIPTION The AD9252 is an octal, 14-bit, 50 MSPS ADC with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. Operating at a conversion rate of up to 50 MSPS, it is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO) for capturing data on the output and a frame clock (FCO) for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes less than 2 mW when all channels are disabled. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. Octal, 14-Bit, 50 MSPS, Serial LVDS, 1.8 V ADC AD9252 FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD DRGND VIN + A VIN – A VIN + B VIN – B VIN + C VIN – C VIN + D VIN – D VIN + E VIN – E VIN + F VIN – F VIN + G VIN – G VIN + H VIN – H VREF SENSE REFT REFB AD9252 ADC ADC ADC ADC ADC ADC ADC ADC REF SELECT 0.5V SERIAL PORT INTERFACE 14 SERIAL LVDS 14 SERIAL LVDS 14 SERIAL LVDS 14 SERIAL LVDS 14 SERIAL LVDS 14 SERIAL LVDS 14 SERIAL LVDS 14 SERIAL LVDS DATA RATE MULTIPLIER D+A D–A D+B D–B D+C D–C D+D D–D D+E D–E D+F D–F D+G D–G D+H D–H FCO+ FCO– DCO+ DCO– RBIAS AGND CSB SDIO/ SCLK/ ODM DTP Figure 1. CLK+ CLK– The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user- defined test patterns entered via the serial port interface (SPI). The AD9252 is available in an RoHS compliant, 64-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C. PRODUCT HIGHLIGHTS 1. Small Footprint. Eight ADCs are contained in a small package. 2. Low Power of 93.5 mW per Channel at 50 MSPS. 3. Ease of Use. A data clock output (DCO) operates up to 350 MHz and supports double data rate (DDR) operation. 4. User Flexibility. SPI control offers a wide range of flexible features to meet specific system requirements. 5. Pin-Compatible Family. This includes the AD9212 (10-bit) and AD9222 (12-bit). One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved. 1 page AD9252 Data Sheet AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 2. Parameter1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz WORST HARMONIC (SECOND OR THIRD) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz WORST OTHER (EXCLUDING SECOND OR THIRD) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS fIN1 = 15 MHz, fIN2 = 16 MHz fIN1 = 70 MHz, fIN2 = 71 MHz Temperature Min Full Full 71 Full Full Full Full 70.2 Full Full Full Full 11.5 Full Full Full Full 73 Full Full Full Full Full Full Full Full Full Full 25°C 25°C AD9252-50 Typ Max 73.2 73 72.7 71 72.5 72.2 72 70.5 11.87 11.84 11.79 11.5 85 84 83 79 −85 −84 −73 −83 −79 −90 −90 −80 −90 −89 80.0 80.0 Unit dB dB dB dB dB dB dB dB Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Rev. E \| Page 4 of 52 5 Page AD9252 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AVDD 1 VIN + G 2 VIN – G 3 AVDD 4 VIN – H 5 VIN + H 6 AVDD 7 AVDD 8 CLK– 9 CLK+ 10 AVDD 11 AVDD 12 DRGND 13 DRVDD 14 D – H 15 D + H 16 PIN 1 INDICATOR EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) AD9252 TOP VIEW (Not to Scale) 48 AVDD 47 VIN + B 46 VIN – B 45 AVDD 44 VIN – A 43 VIN + A 42 AVDD 41 PDWN 40 CSB 39 SDIO/ODM 38 SCLK/DTP 37 AVDD 36 DRGND 35 DRVDD 34 D + A 33 D – A NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND Figure 5. 64-Lead LFCSP Pin Configuration, Top View Table 7. Pin Function Descriptions Pin No. Mnemonic 0 AGND 1, 4, 7, 8, 11, 12, 37, 42, 45, 48, 51, 59, 62 AVDD 13, 36 DRGND 14, 35 DRVDD 2 VIN + G 3 VIN − G 5 VIN − H 6 VIN + H 9 CLK− 10 CLK+ 15 D − H 16 D + H 17 D − G 18 D + G 19 D − F 20 D + F 21 D − E 22 D + E 23 DCO− 24 DCO+ 25 FCO− 26 FCO+ 27 D − D 28 D + D 29 D − C 30 D + C 31 D − B Description Analog Ground (Exposed Paddle) 1.8 V Analog Supply Digital Output Driver Ground 1.8 V Digital Output Driver Supply ADC G Analog Input True ADC G Analog Input Complement ADC H Analog Input Complement ADC H Analog Input True Input Clock Complement Input Clock True ADC H Digital Output Complement ADC H Digital Output True ADC G Digital Output Complement ADC G Digital Output True ADC F Digital Output Complement ADC F Digital Output True ADC E Digital Output Complement ADC E Digital Output True Data Clock Digital Output Complement Data Clock Digital Output True Frame Clock Digital Output Complement Frame Clock Digital Output True ADC D Digital Output Complement ADC D Digital Output True ADC C Digital Output Complement ADC C Digital Output True ADC B Digital Output Complement Rev. E \| Page 10 of 52 Data Sheet 11 Page

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