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PDF AT91FR40162S Data sheet ( Hoja de datos )
| Número de pieza | AT91FR40162S | |
| Descripción | MicroControllers | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Incorporates the ARM7TDMI® ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Embedded ICE (In-circuit Emulation)
• 256K Bytes of On-chip SRAM
– 32-bit Data Bus, Single-clock Cycle Access
• 1024K Words 16-bit Flash Memory (2M bytes)
– Single Voltage Read/Write,
– Sector Erase Architecture
– Erase Suspend Capability
– Low-power Operation
– Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection
– Reset Input for Device Initialization
– Sector Program Unlock Command
– 128-bit Protection Register
– Factory-programmed AT91 Flash Memory Uploader Software
• Fully Programmable External Bus Interface (EBI)
– Up to 8 Chip Selects, Maximum External Address Space of 64M Bytes
– Software Programmable 8/16-bit External Data Bus
• 8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 4 External Interrupts, Including a High-priority Low-latency Interrupt Request
• 32 Programmable I/O Lines
• 3-channel 16-bit Timer/Counter
– 3 External Clock Inputs, 2 Multi-purpose I/O Pins per Channel
• 2 USARTs
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
• Programmable Watchdog Timer
• Advanced Power-saving Features
– CPU and Peripherals Can be De-activated Individually
• Fully Static Operation:
– 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.8V, 85° C
• 2.7V to 3.6V I/O Operating Range, 1.65V to 1.95V Core Operating Range
• -40° C to 85° C Temperature Range
• Available in a 121-ball 10 x 10 x 1.2 mm BGA Package with 0.8 mm Ball Pitch
AT91 ARM®
Thumb®
Microcontrollers
AT91FR40162S
Summary
Preliminary
1. Description
The AT91FR40162S is a member of the Atmel AT91 16/32-bit Microcontroller family,
which is based on the ARM7TDMI processor core. The processor has a high-perfor-
mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low
power consumption.
The AT91FR40162S ARM microcontroller features 2 Mbits of on-chip SRAM and 2
Mbytes of Flash memory in a single compact 121-ball BGA package. Its high level of
integration and very small footprint make the device ideal for space-constrained appli-
cations. The high-speed on-chip SRAM enables a performance of up to 74 MIPs in
typical conditions with significant power reduction and EMC improvement over an
external SRAM implementation.
The Flash memory may be programmed via the JTAG/ICE interface or the factory-
programmed Flash Memory Uploader (FMU) using a single device supply, making the
AT91FR40162S suitable for in-system programmable applications.
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4. Block Diagram
Figure 4-1. AT91FR40162S
AT91FR40162S
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AT91FR40162S
6.6.6
The External Bus Interface features also the Early Read Protocol, configurable for all the
devices, that significantly reduces access time requirements on an external device in the case
of single-clock cycle access.
In the AT91FR40162S, the External Bus Interface connects internally to the Flash memory.
Flash Memory
The 2-Mbyte Flash memory is organized as 1, 048, 576 words of 16 bits each. The Flash
memory is addressed as 16-bit words via the EBI. It uses address lines A1 - A20 of the
processor.
The address, data and control signals, except the Flash memory enable, are internally inter-
connected. The user should connect the Flash memory enable (NCSF) to one of the active-
low chip selects on the EBI; NCS0 must be used if the Flash memory is to be the boot mem-
ory. In addition, if the Flash memory is to be used as boot memory, the BMS input must be
pulled down externally in order for the processor to perform correct 16-bit fetches after reset.
During boot, the EBI must be configured with correct number of standard wait states. As an
example, five standard wait states are required when the microcontroller is running at 66 MHz.
The user must ensure that all VDDIO, VDDCORE and all GND pins are connected to their
respective supplies by the shortest route. The Flash memory powers-on in read mode. Com-
mand sequences are used to place the device in other operating modes, such as program and
erase.
A separate Flash memory reset input pin (NRSTF) is provided for maximum flexibility,
enabling the reset operation to adapt to the application. When this input is at a logic high level,
the memory is in its standard operating mode; a low level on this input halts the current mem-
ory operation and puts its outputs in a high impedance state.
The Flash memory features data polling to detect the end of a program cycle. While a program
cycle is in progress, an attempted read of the last word written will return the complement of
the written data on I/O7. An open-drain NBUSY output pin provides another method of detect-
ing the end of a program or erase cycle. This pin is pulled low while program and erase cycles
are in progress and is released at the completion of the cycle. A toggle bit feature provides a
third means of detecting the end of a program or erase cycle.
The Flash memory is divided into 39 sectors for erase operations. To further enhance device
flexibility, an Erase Suspend feature is offered. This feature puts the erase cycle on hold for an
indefinite period and allows the user to read data from, or to write data to, any other sector
within the same memory plane. There is no need to suspend an erase cycle if the data to be
read is in the other memory plane.
The device has the capability to protect data stored in any sector. Once the data protection for
a sector is enabled, the data in that sector cannot be changed while input levels lie between
ground and VDDIO.
Note: This data protection does not prevent read accesses of the FLASH.
An optional VPP pin is available to enhance program/erase times.
A 6-byte command sequence (Enter Single Pulse Program Mode) allows the device to be writ-
ten to directly, using single pulses on the write control lines. This mode (Single-pulse
Programming) is exited by powering down the device or by pulsing the NRSTF pin low for a
defined duration and then bringing it back to VDDIO.
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| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet AT91FR40162S.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AT91FR40162 | AT91 ARM Thumb Microcontrollers | ATMEL Corporation |
| AT91FR40162-CI | AT91 ARM Thumb Microcontrollers | ATMEL Corporation |
| AT91FR40162S | MicroControllers | ATMEL Corporation |
| AT91FR40162SB | AT91 ARM Thumb-based Microcontrollers | ATMEL Corporation |
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