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PDF ADE7763 Data sheet ( Hoja de datos )
| Número de pieza | ADE7763 | |
| Descripción | Single-Phase Active and Apparent Energy Metering IC | |
| Fabricantes | Analog Devices | |
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Single-Phase Active and Apparent
Energy Metering IC
ADE7763
FEATURES
High accuracy; supports IEC 61036/60687, IEC62053-21, and
IEC62053-22
On-chip digital integrator enables direct interface-to-current
sensors with di/dt output
A PGA in the current channel allows direct interface to
shunts and current transformers
Active and apparent energy, sampled waveform, and current
and voltage rms
Less than 0.1% error in active energy measurement over a
dynamic range of 1000 to 1 at 25°C
Positive-only energy accumulation mode available
On-chip user programmable threshold for line voltage surge
and SAG and PSU supervisory
Digital calibration for power, phase, and input offset
On-chip temperature sensor (±3°C typical)
SPI®-compatible serial interface
Pulse output with programmable frequency
Interrupt request pin (IRQ) and status register
Reference 2.4 V with external overdrive capability
Single 5 V supply, low power (25 mW typical)
GENERAL DESCRIPTION
The ADE77631 features proprietary ADCs and fixed function
DSP for high accuracy over large variations in environmental
conditions and time. The ADE7763 incorporates two second-
order, 16-bit Σ-∆ ADCs, a digital integrator (on Ch1), reference
circuitry, a temperature sensor, and all the signal processing
required to perform active and apparent energy measurements,
line-voltage period measurements, and rms calculation on the
voltage and current channels. The selectable on-chip digital
integrator provides direct interface to di/dt current sensors such
as Rogowski coils, eliminating the need for an external analog
integrator and resulting in excellent long-term stability and
precise phase matching between the current and the voltage
channels.
The ADE7763 provides a serial interface to read data and a
pulse output frequency (CF) that is proportional to the active
power. Various system calibration features such as channel
offset correction, phase calibration, and power calibration
ensure high accuracy. The part also detects short duration, low
or high voltage variations.
The positive-only accumulation mode gives the option to
accumulate energy only when positive power is detected. An
internal no-load threshold ensures that the part does not exhibit
any creep when there is no load. The zero-crossing output (ZX)
produces a pulse that is synchronized to the zero-crossing point
of the line voltage. This signal is used internally in the line cycle
active and apparent energy accumulation modes, which enables
faster calibration.
The interrupt status register indicates the nature of the interrupt,
and the interrupt enable register controls which event produces
an output on the IRQ pin, an open-drain, active low logic output.
The ADE7763 is available in a 20-lead SSOP package.
FUNCTIONAL BLOCK DIAGRAM
AVDD
PGA
V1P
ADC
V1N
TEMP
SENSOR
RESET
DVDD DGND
INTEGRATOR
MULTIPLIER
dt
LPF2
WGAIN[11:0]
HPF1
IRMSOS[11:0]
APOS[15:0]
ADE7763
CFNUM[11:0]
PGA
V2P
V2N
ADC
Φ
PHCAL[5:0] LPF1
2.4V
4kΩ
REFERENCE
x2
VRMSOS[11:0]
x2
VAGAIN[11:0]
DFC
CF
CFDEN[11:0]
VADIV[7:0]
%%
WDIV[7:0]
REGISTERS AND
SERIAL INTERFACE
ZX
SAG
AGND
REFIN/OUT
CLKIN CLKOUT
DIN DOUT SCLK CS IRQ
1U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; others pending.
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
ADE7763
TIMING CHARACTERISTICS
AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL, TMIN to TMAX = −40°C to +85°C.
Table 2. Timing Characteristics1, 2
Parameter
Spec
Unit
Test Conditions/Comments
Write Timing
t1
t2
t3
t4
t5
t6
t7
t8
50
50
50
10
5
400
50
100
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min)
CS falling edge to first SCLK falling edge.
SCLK logic high pulse width.
SCLK logic low pulse width.
Valid data setup time before falling edge of SCLK.
Data hold time after SCLK falling edge.
Minimum time between the end of data byte transfers.
Minimum time between byte transfers during a serial write.
CS hold time after SCLK falling edge.
Read Timing
t93
4
µs min
Minimum time between read command (i.e., a write to
communication register) and data read.
t10
50
ns min
Minimum time between data byte transfers during a multibyte read.
t11
30
ns min
Data access time after SCLK rising edge following a write to the
communication register.
t124
100
ns max
Bus relinquish time after falling edge of SCLK.
10 ns min
t135
100
ns max
Bus relinquish time after rising edge of CS.
10 ns min
________________________________________________
1 Sample tested during initial release and after any redesign or process change that could affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to
90%) and timed from a voltage level of 1.6 V.
2 See Figure 3, Figure 4, and the Serial Interface section.
3 Minimum time between read command and data read for all registers except waveform register, which is t9 = 500 ns min.
4 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
5 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of
the part and is independent of the bus loading.
t8
CS
SCLK
DIN
t1
1
t3
t7
t2
t4
t5
0 A5 A4 A3 A2 A1 A0
DB7
t6
t7
DB0
DB7
DB0
COMMAND BYTE
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
CS
SCLK
t1
Figure 3. Serial Write Timing
t9
t10
t13
DIN
DOUT
0 0 A5 A4 A3 A2 A1 A0
t11
DB7
t11
DB0
COMMAND BYTE
MOST SIGNIFICANT BYTE
Figure 4. Serial Read Timing
DB7
t12
DB0
LEAST SIGNIFICANT BYTE
Rev. A | Page 5 of 56
5 Page 
1.2
GAIN = 8
1.0 INTEGRATOR OFF
INTERNAL REFERENCE
0.8
0.6
PF = 0.5
0.4
0.2
PF = 1
0
–0.2
–0.4
–0.6
45 47 49 51 53 55 57 59 61 63 65
FREQUENCY (Hz)
Figure 12. Active Energy Error as a Percentage of Reading (Gain = 8)
over Frequency with Internal Reference and Integrator Off
1.0
0.8 GAIN = 8
INTEGRATOR OFF
0.6 INTERNAL REFERENCE
0.4
0.2
0
–0.2
PF = 1
PF = 0.5
–0.4
–0.6
–0.8
–1.0
0.1
1 10
FULL-SCALE CURRENT (%)
100
Figure 13. IRMS Error as a Percentage of Reading (Gain = 8)
with Internal Reference and Integrator Off
0.5
GAIN = 1
0.4 EXTERNAL REFERENCE
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
1
10
FULL-SCALE VOLTAGE (%)
100
Figure 14. VRMS Error as a Percentage of Reading (Gain = 1)
with External Reference
ADE7763
1.0
0.8 GAIN = 8
INTEGRATOR ON
0.6 INTERNAL REFERENCE
0.4
+85°C, PF = 0.5
0.2
0
–0.2
+25°C, PF = 0.5
+25°C, PF = 1
–0.4
–0.6
–40°C, PF = 0.5
–0.8
–1.0
0.1
1 10
FULL-SCALE CURRENT (%)
100
Figure 15. Active Energy Error as a Percentage of Reading (Gain = 8)
over Power Factor with Internal Reference and Integrator On
1.0
0.8 GAIN = 8
INTEGRATOR ON
0.6 INTERNAL REFERENCE
0.4
+85°C, PF = 1
0.2
0
–0.2
+25°C, PF = 1
–0.4
–0.6
–40°C, PF = 1
–0.8
–1.0
0.1
1 10
FULL-SCALE CURRENT (%)
100
Figure 16. Active Energy Error as a Percentage of Reading (Gain = 8)
over Temperature with External Reference and Integrator On
3.0
2.5
2.0
PF = 0.5
1.5
GAIN = 8
INTEGRATOR ON
INTERNAL REFERENCE
1.0
0.5
0 PF = 1
–0.5
–1.0
–1.5
–2.0
45 47 49 51 53 55 57 59 61 63 65
FREQUENCY (Hz)
Figure 17. Active Energy Error as a Percentage of Reading (Gain = 8)
over Frequency with Internal Reference and Integrator On
Rev. A | Page 11 of 56
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADE7763.PDF ] | |
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