PDF AD7021 Data sheet ( Hoja de datos )

Número de pieza	AD7021
Descripción	High Performance Narrowband ISM Transceiver IC
Fabricantes	Analog Devices
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No Preview Available ! www.DataSheet4U.com Preliminary Technical Data High Performance Narrowband ISM Transceiver IC ADF7021 FEATURES Low power, low IF transceiver Frequency bands 80 MHz to 650 MHz 862 MHz to 940 MHz Modulation schemes 2FSK, 3FSK, 4FSK Spectral shaping Gaussian and raised-cosine filtering Data rates supported 0.05 kbps to 25 kbps 2.3 V to 3.6 V power supply Programmable output power −16 dBm to +13 dBm in 63 steps Automatic PA ramp control Receiver sensitivity −125 dBm at 1 kbps, 2 FSK On-chip VCO and fractional-N PLL RSET On-chip 7-bit ADC and temperature sensor Fully automatic frequency control loop (AFC) Digital RSSI Integrated Tx/Rx switch Leakage current <1 μA in power-down mode APPLICATIONS Narrow-band standards ETSI EN 300-220, FCC Part 90, FCC Part 15, FCC Part 95, ARIB STD-T67 Low cost, wireless data transfer Remote control/security systems Wireless metering Private mobile radio Wireless medical telemetry service (WMTS) Keyless entry Home automation Process and building control Pagers FUNCTIONAL BLOCK DIAGRAM CE CREG(1:4) MUXOUT RLNA POLARIZATION TEMP SENSOR MUX 7-BIT ADC LDO(1:4) TEST MUX RFIN RFINB LNA GAIN IF FILTER RSSI/ OFFSET CORRECTION 2FSK 3FSK 4FSK DEMODULATOR CLOCK AND DATA RECOVERY Tx/Rx CONTROL PA RAMP RFOUT DIVIDERS/ MUXING MUX VCO AGC CONTROL AFC CONTROL SERIAL PORT DIV P N/N + 1 Σ-Δ MODULATOR 2FSK 3FSK 4FSK MOD CONTROL CP PFD DIV R RING OSC CLK DIV GAUSSIAN/ RAISED COSINE FILTER 3FSK ENCODING L1 L2 VCOIN CPOUT OSC1 OSC2 Figure 1. CLKOUT DATA CLK \| TxDATA DATA I/O \| RxDATA SWD SLE SDATA SREAD SCLK Rev. PrI Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. DataSheet4 U .com One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. 1 page www.DataSheet4U.com Preliminary Technical Data Parameter CHANNEL FILTERING Adjacent Channel Rejection (Offset = ±1 × IF Filter BW Setting) Second Adjacent Channel Rejection (Offset = ±2 × IF Filter BW Setting) Third Adjacent Channel Rejection (Offset = ±3 × IF Filter BW Setting) Image Channel Rejection Co-Channel Rejection Wideband Interference Rejection BLOCKING ±1 MHz ±5 MHz ±10 MHz ±10 MHz (High Linearity Mode) Saturation (Maximum Input Level) LNA Input Impedance Min RECEIVE SIGNAL STRENGTH INDICATOR (RSSI) Range at Input Linearity Absolute Accuracy Response Time PHASE-LOCKED LOOP (PLL) VCO Gain Phase Noise (In-Band) Phase Noise (Out-of-Band) Residual FM PLL Settling REFERENCE INPUT Crystal Reference External Oscillator Load Capacitance Crystal Start-Up Time Input Level ADC PARAMETERS INL DNL TIMING INFORMATION Chip Enabled to Regulator Ready Chip Enabled to RSSI Ready Tx to Rx Turnaround Time 3.625 3.625 DataSheet4 U .com ADF7021 Typ Max Unit Test Conditions 27 dB IF filter BW setting = 12.5 kHz, 18.75 kHz, 25 kHz 50 dB Desired signal 3 dB above the input sensitivity level, CW interferer power level 55 dB Increased until BER = 10−3, image channel excluded 35 dB Image at FRF − 200 kHz −3 dB 70 dB Swept from 100 MHz to 2 GHz, measured as channel rejection 60 68 65 72 12 24 − j60 26 − j63 71 − j128 dB dB dB dB dBm Ω Ω Ω Desired signal 3 dB above the input sensitivity level, CW interferer power level Increased until BER = 10−2 FSK mode, BER = 10−3 FRF = 915 MHz, RFIN to GND FRF = 868 MHz FRF = 433 MHz −110 to −36 ±2 ±3 150 dBm dB dB μs See the RSSI/AGC section 65 130 65 −99 −113 128 40 MHz/V MHz/V MHz/V dBc/Hz dBc/Hz Hz μs 902 MHz to 928 MHz band, VCO adjust = 0, VCO_BIAS_SETTING = 8 860 MHz to 870 MHz band, VCO adjust = 0 433 MHz, VCO adjust = 0 PA = 10 dBm, VDD = 3.0 V, PFD = 24.57 MHz, FRF = 433 MHz, VCO_BIAS_SETTING = 15 1 MHz offset From 200 Hz to 20 kHz, FRF = 868 MHz Measured for a 10 MHz frequency step to within 5 ppm accuracy, PFD = 20 MHz, loop bandwidth (LBW) = 50 kHz TBD MHz TBD MHz 33 pF PC board layout and crystal specific 2.1 ms 11.0592 MHz crystal, using 33 pF load capacitors CMOS levels See the Reference Input section ±1 LSB From 2.3 V to 3.6 V, TA = 25°C ±1 LSB From 2.3 V to 3.6 V, TA = 25°C 10 3.0 150 μs + (5 × TBIT) μs CREG = 100 nF ms See Table 14 for more details Time to synchronized data out, includes AGC settling; see AGC Information and Timing section for more details Rev. PrI \| Page 5 of 44 5 Page www.DataSheet4U.com Preliminary Technical Data ADF7021 Pin No. Mnemonic 28 SCLK 29 GND2 30 ADCIN 31 CREG2 32 VDD2 33 SWD 34 DATA I/O \| RxDATA 35 DATA CLK \| TxDATA 36 CLKOUT 37 MUXOUT 38 39 40 41 42 43 44, 46 OSC2 OSC1 VDD3 CREG3 CPOUT VDD L2, L1 45, 47 48 GND, GND1 CVCO Function Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This pin is a digital CMOS input. Ground for Digital Section. Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 V to 1.9 V. Readback is made using the SREAD pin. Regulator Voltage for Digital Block. A 100 nF capacitor should be placed between this pin and ground for regulator stability and noise rejection. Voltage Supply for Digital Block. A decoupling capacitor of 10 nF should be placed as close as possible to this pin. Sync Word Detect. The ADF7021 asserts this pin when it has found a match for the sync word sequence (See the Register 11—Sync Word Detect Register section). This provides an interrupt for an external microcontroller indicating valid data is being received. Transmit Data Input/Received Data Output. This is a digital pin and normal CMOS levels apply. In UART mode, this pin provides an output for the received data in receive mode. In transmit mode, this pin is high impedance (see the Register 0—N Register section). Outputs the data clock in both receive and transmit modes. This is a digital pin and normal CMOS levels apply. The positive clock edge is matched to the center of the received data. In transmit mode, this pin outputs an accurate clock to latch the data from the microcontroller into the transmit section at the exact required data rate. In UART mode, this pin is used to input the transmit data in transmit mode. In receive mode, this pin is high impedance (see the Register 0—N Register section). A Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used to drive several other CMOS inputs such as a microcontroller clock. The output has a 50:50 mark-space ratio. Provides the Lock_Detect Signal. This signal is used to determine if the PLL is locked to the correct frequency. Other signals include Regulator_Ready, which is an indicator of the status of the serial interface regulator (see the Register 0—N Register section). The reference crystal should be connected between this pin and OSC1. A TCXO reference can be used by driving this pin with CMOS levels and disabling the crystal oscillator. The reference crystal should be connected between this pin and OSC2. Voltage Supply for the Charge Pump and PLL Dividers. This pin should be decoupled to ground with a 10 nF capacitor. Regulator Voltage for Charge Pump and PLL Dividers. A 100 nF capacitor should be placed between this pin and ground for regulator stability and noise rejection. Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO. Voltage Supply for VCO Tank Circuit. This pin should be decoupled to ground with a 10 nF capacitor. External VCO Inductor Pins. If using an external VCO inductor, a chip inductor should be connected across these pins to set the VCO operating frequency. If using the internal VCO inductor, these pins can be left floating. See the Voltage Controlled Oscillator (VCO) section for more information. Grounds for VCO Block. A 22 nF capacitor should be placed between this pin and CREG1 to reduce VCO noise. DataSheet4 U .com Rev. PrI \| Page 11 of 44 11 Page

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