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PDF AT49BV161 Data sheet ( Hoja de datos )
| Número de pieza | AT49BV161 | |
| Descripción | (AT49xV160 / AT49xV161) Flash Memory | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Single Voltage Read/Write Operation: 2.65V to 3.3V (BV), 3.0V to 3.6V (LV)
• Access Time – 70 ns
• Sector Erase Architecture
– Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout
– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout
• Fast Word Program Time – 20 µs
• Fast Sector Erase Time – 300 ms
• Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming from Any Sector by Suspending Erase of a
Different Sector
– Supports Reading Any Byte/Word by Suspending Programming of Any Other
Byte/Word
• Low-power Operation
– 30 mA Active
– 10 µA Standby
• Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
• VPP Pin for Write Protection and Accelerated Program/Erase Operations
• RESET Input for Device Initialization
• Sector Lockdown Support
• TSOP and CBGA Package Options
• Top or Bottom Boot Block Configuration Available
• 128-bit Protection Register
Description
The AT49BV/LV16X(T) is a 3.0-volt 16-megabit Flash memory organized as 1,048,576
words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data appears on I/O0
- I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided into 39 sectors for
erase operations. The device is offered in a 48-lead TSOP, 45-ball and 48-ball CBGA
packages. The device has CE and OE control signals to avoid any bus contention.
This device can be read or reprogrammed using a single 2.65V power supply, making
it ideally suited for in-system programming.
Pin Configurations
Pin Name
A0 - A19
CE
OE
WE
RESET
RDY/BUSY
VPP
I/O0 - I/O14
I/O15 (A-1)
BYTE
NC
VCCQ
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
READY/BUSY Output
Write Protection and Power Supply for Accelerated Program/Erase
Operations
Data Inputs/Outputs
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
Selects Byte or Word Mode
No Connect
Output Power Supply
16-megabit
(1M x 16/2M x 8)
3-volt Only
Flash Memory
AT49BV160
AT49LV160
AT49BV160T
AT49BV161
AT49LV161
AT49BV161T
AT49LV161T
Rev. 1427L–FLASH–02/03
1
1 page  
Device
Operation
AT49BV/LV160(T)/161(T)
READ: The AT49BV/LV16X(T) is accessed like an EPROM. When CE and OE are low and
WE is high, the data stored at the memory location determined by the address pins are
asserted on the outputs. The outputs are put in the high-impedance state whenever CE or OE
is high. This dual-line control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES: When the device is first powered on, it will be reset to the read or
standby mode, depending upon the state of the control line inputs. In order to perform other
device functions, a series of command sequences are entered into the device. The command
sequences are shown in the “Command Definition in Hex” table on page 13 (I/O8 - I/O15 are
don’t care inputs for the command codes). The command sequences are written by applying a
low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address
is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the
first rising edge of CE or WE. Standard microprocessor write timings are used. The address
locations used in the command sequences are not affected by entering the command
sequences.
RESET: A RESET input pin is provided to ease some system applications. When RESET is at
a logic high level, the device is in its standard operating mode. A low level on the RESET input
halts the present device operation and puts the outputs of the device in a high-impedance
state. When a high level is reasserted on the RESET pin, the device returns to the read or
standby mode, depending upon the state of the control inputs.
ERASURE: Before a byte/word can be reprogrammed, it must be erased. The erased state of
memory bits is a logical “1”. The entire device can be erased by using the Chip Erase com-
mand or individual sectors can be erased by using the Sector Erase command.
CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase
software code. After the chip erase has been initiated, the device will internally time the erase
operation so that no external clocks are required. The maximum time to erase the chip is tEC.
If the sector lockdown has been enabled, the chip erase will not erase the data in the sector
that has been locked out; it will erase only the unprotected sectors. After the chip erase, the
device will return to the read or standby mode.
SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 39 sec-
tors (SA0 - SA38) that can be individually erased. The Sector Erase command is a six-bus
cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while
the 30H data input command is latched on the rising edge of WE. The sector erase starts after
the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will
automatically time to completion. The maximum time to erase a sector is tSEC. When the sec-
tor programming lockdown feature is not enabled, the sector will erase (from the same Sector
Erase command). An attempt to erase a sector that has been protected will result in the oper-
ation terminating in 2 µs.
BYTE/WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logi-
cal “0”) on a byte-by-byte or on a word-by-word basis. Programming is accomplished via the
internal device command register and is a four-bus cycle operation. The device will automati-
cally generate the required internal program pulses.
1427L–FLASH–02/03
5
5 Page 
Figure 3. Toggle Bit Algorithm
(Configuration Register = 00)
START
Read I/O7 - I/O0
Read I/O7 - I/O0
AT49BV/LV160(T)/161(T)
Figure 4. Toggle Bit Algorithm
(Configuration Register = 01)
START
Read I/O7 - I/O0
Read I/O7 - I/O0
Toggle Bit =
Toggle?
NO
YES
NO I/O3, I/O5 = 1?
YES
Read I/O7 - I/O0
Twice
Toggle Bit =
Toggle?
NO
YES
NO I/O3, I/O5 = 1?
YES
Read I/O7 - I/O0
Twice
Toggle Bit =
Toggle?
NO
YES
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Program/Erase
Operation
Successful
Note:
1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
Toggle Bit =
Toggle?
NO
YES
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Program/Erase
Operation
Successful,
Write Product ID
Exit Command
Note:
1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
1427L–FLASH–02/03
11
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| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet AT49BV161.PDF ] | |
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