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PDF AT89C51IC2 Data sheet ( Hoja de datos )
| Número de pieza | AT89C51IC2 | |
| Descripción | 8-bit Flash Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• 80C52 Compatible
– 8051 Pin and Instruction Compatible
– Four 8-bit I/O ports + 2 I/O 2-wire Interface (TWI) Pins
– Three 16-bit Timer/Counters
– 256 bytes Scratch Pad RAM
– 10 Interrupt Sources with 4 Priority Levels
– Dual Data Pointer
• Variable Length MOVX for Slow RAM/Peripherals
• ISP (In-System-Programming) Using Standard Vcc Power Supply
• Boot ROM Contains Low Level Flash Programming Routines and a Default Serial
Loader
• High-speed Architecture
– In Standard Mode:
40 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
– In X2 mode (6 Clocks/machine cycle)
20 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
– 32K Bytes On-chip Flash Program/Data Memory
– Byte and Page (128 Bytes) Erase and Write
– 100K Write Cycles
• On-chip 1024 Bytes Expanded RAM (XRAM)
– Software Selectable Size (0, 256, 512, 768, 1024 Bytes)
– 256 Bytes Selected at Reset for TS87C51RB2/RC2 Compatibility
• Keyboard Interrupt Interface on Port P1
• 400-Kbits/s Multimaster 2-wire Interface
• SPI Interface (Master/Slave Mode)
• Sub-clock 32 kHz Crystal Oscillator
• 8-bit clock Prescaler
• Improved X2 Mode With Independant Selection for CPU and Each Peripheral
• Programmable Counter Array 5 Channels with:
– High Speed Output
– Compare/Capture
– Pulse Width Modulator
– Watchdog Timer Capabilities
• Asynchronous Port Reset
• Full-duplex Enhanced UART
• Dedicated Baud Rate Generator for UART
• Low EMI (Inhibit ALE)
• Hardware Watchdog Timer (One-time enabled with Reset-Out)
• Power Control Modes:
– Idle Mode
– Power-down Mode
– Power-Off Flag
• Power Supply:
– 2.7 to 3.6 (3V Version)
– 2.7 to 5.5V (5V Version)
• Temperature Ranges: Commercial (0 to +70°C) and Industrial (-40°C to +85°C)
• Packages: PLC44, VQFP44
8-bit Flash
Microcontroller
with 2-wire
Interface
AT89C51IC2
Rev. 4301D–8051–02/08
1
1 page  
AT89C51IC2
Table 2. C51 Core SFRs
Mnemonic Add Name
ACC
E0h Accumulator
B F0h B Register
PSW
D0h Program Status Word
SP 81h Stack Pointer
DPL
82h Data Pointer Low byte
DPH
83h Data Pointer High byte
Table 3. System Management SFRs
Mnemonic Add Name
PCON
87h Power Control
AUXR
8Eh Auxiliary Register 0
AUXR1
CKRL
CKSEL
OSCON
CKCKON0
CKCKON1
A2h Auxiliary Register 1
97h Clock Reload Register
85h Clock Selection Register
86h Oscillator Control Register
8Fh Clock Control Register 0
AFh Clock Control Register 1
76543210
CY AC F0 RS1 RS0 OV F1
P
76
SMOD1 SMOD0
5
-
4
-
- - M0
-
-
-
-
TWIX2
-
-
-
-
-
WDTX2
-
ENBOO
T
-
-
-
PCAX2
-
-
-
-
-
SIX2
-
3
GF1
XRS1
2
GF0
XRS0
1
PD
EXTRA
M
0
IDL
AO
GF3 0
- DPS
-
-
-
T2X2
-
---
- - CKS
SCLKT0 OscBEn OscAEn
T1X2
T0X2
X2
- - SPIX2
Table 4. Interrupt SFRs
Mnemonic Add Name
76543210
IEN0
A8h Interrupt Enable Control 0
EA EC ET2 ES ET1 EX1 ET0 EX0
IEN1
B1h Interrupt Enable Control 1
-
-
-
-
-
ESPI
ETWI
KBD
IPH0
B7h Interrupt Priority Control High 0
-
PPCH
PT2H
PHS
PT1H
PX1H
PT0H
PX0H
IPL0
B8h Interrupt Priority Control Low 0
-
PPCL
PT2L
PLS
PT1L
PX1L
PT0L
PX0L
IPH1
B3h Interrupt Priority Control High 1
-
-
-
-
-
SPIH
TWIH KBDH
IPL1
B2h Interrupt Priority Control Low 1
-
-
-
-
-
SPIL
TWIL
KBDL
4301D–8051–02/08
5
5 Page 
AT89C51IC2
Table 13. Pin Description for 40/44 Pin Packages
Mnemonic
VSS
VCC
P0.0 - P0.7
P1.0 - P1.7
Pin Number
PLCC44
VQFP44 1.4
22 16
44 38
43 - 36
37 - 30
2-9
40 - 44
1-3
2 40
3 41
4 42
5 43
6 44
71
82
Type
I
I
I/O
I/O
I/O
I/O
I
I/O
I
I
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Name and Function
Ground: 0V reference
Power Supply: This is the power supply voltage for normal, idle and power-down
operation
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high impedance inputs. Port 0 must be polarized to VCC
or VSS in order to prevent any parasitic current consumption. Port 0 is also the multi-
plexed low-order address and data bus during access to external program and data
memory. In this application, it uses strong internal pull-up when emitting 1s. Port 0 also
inputs the code bytes during EPROM programming. External pull-ups are required dur-
ing program verification during which P0 outputs the code bytes.
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 1 pins that are externally pulled low will source current because
of the internal pull-ups. Port 1 also receives the low-order address byte during memory
programming and verification.
Alternate functions for AT89C51IC2 Port 1 include:
P1.0: Input/Output
T2 (P1.0): Timer/Counter 2 external count input/Clockout
XTALB1 (P1.0): Sub Clock input to the inverting oscillator amplifier
P1.1: Input/Output
T2EX: Timer/Counter 2 Reload/Capture/Direction Control
SS: SPI Slave Select
P1.2: Input/Output
ECI: External Clock for the PCA
P1.3: Input/Output
CEX0: Capture/Compare External I/O for PCA module 0
P1.4: Input/Output
CEX1: Capture/Compare External I/O for PCA module 1
P1.5: Input/Output
CEX2: Capture/Compare External I/O for PCA module 2
MISO: SPI Master Input Slave Output line
When SPI is in master mode, MISO receives data from the slave peripheral. When SPI
is in slave mode, MISO outputs data to the master controller.
P1.6: Input/Output
CEX3: Capture/Compare External I/O for PCA module 3
SCK: SPI Serial Clock
SCK outputs clock to the slave peripheral
4301D–8051–02/08
11
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