|
|
PDF ISL1219 Data sheet ( Hoja de datos )
| Número de pieza | ISL1219 | |
| Descripción | Real Time Clock/Calendar | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ISL1219 (archivo pdf) en la parte inferior de esta página. Total 25 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
ISL1219
®
Real Time Clock/Calendar with Event Detection
Data Sheet
August 14, 2006
FN6314.1
Low Power RTC with Battery Backed
SRAM and Event Detection
The ISL1219 device is a low power real time clock with
Event Detect and Time Stamp function, timing and crystal
compensation, clock/calendar, power fail indicator, periodic
or polled alarm, intelligent battery backup switching and 2
Bytes of battery-backed user SRAM.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
Ordering Information
PART
NUMBER
PART
(See Note) MARKING
VDD
RANGE
TEMP
RANGE
(°C)
PACKAGE
(Pb-Free)
ISL1219IUZ 1219Z
2.7V to 5.5V -40 to +85 10 Ld MSOP
ISL1219IUZ-T 1219Z
2.7V to 5.5V -40 to +85 10 Ld MSOP
Tape and Reel
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both
SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout
ISL1219
(10 LD MSOP)
TOP VIEW
X1 1
X2 2
VBAT 3
GND 4
EVIN 5
10 VDD
9 IRQ/FOUT
8 SCL
7 SDA
6 EVDET
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes, and Seconds
- Day of the Week, Day, Month, and Year
• Security and Event Functions
- Tamper detection with Time Stamp in Normal and
Battery Backed modes
- Event Detection During Battery Backed or Normal
Modes
- Selectable Event Input Sampling Rates Allows Low
Power Operation
- Selectable Glitch Filter on Event Input Monitor
• 15 Selectable Frequency Outputs
• Single Alarm
- Settable to the Second, Minute, Hour, Day of the Week,
Day, or Month
- Single Event or Pulse Interrupt Mode
• Automatic Backup to Battery or Super Cap
• Power Failure Detection
• On-Chip Oscillator Compensation
• 2 Bytes Battery-Backed User SRAM
• I2C Interface
- 400kHz Data Transfer Rate
• 400nA Battery Supply Current
• Small Package
- 10 Ld MSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Utility Meters
• Set Top Box/Modem
• POS Equipment
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Test Meters/Fixtures
• Vending Machine Management
• Security and Anti Tampering Applications
- Panel/Enclosure Status
- Warranty Reporting
- Time Stamping Applications
- Patrol/Security Check (Fire or Light Equipment)
- Automotive Applications
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
www.DataSheet4U.com
ISL1219
I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (Note 4) MAX
UNITS NOTES
tF SDA and SCL Fall Time
From 70% to 30% of VDD.
20 +
0.1 x Cb
300 ns
7
Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
400 pF
7
Rpu
SDA and SCL Bus Pull-up Resistor Maximum is determined by tR and tF.
1
Off-chip
For Cb = 400pF, max is about
2~2.5kΩ. For Cb = 40pF, max is about
15~20kΩ
kΩ 7
NOTES:
2. IRQ and FOUT and EVDET Inactive.
3. LPMODE = 0 (default).
4. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
5. Typical values are for T = 25°C and 3.3V supply voltage.
6. VSUP = VDD if in VDD Mode, VSUP = VBAT if in VBAT Mode.
7. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
8. A write to register 08h should only be done if VDD > VBAT, otherwise the device will be unable to communicate using I2C.
SDA vs. SCL Timing
tF
tHIGH
SCL
tSU:STA
SDA
(INPUT TIMING)
tSU:DAT
tHD:STA
SDA
(OUTPUT TIMING)
tLOW
tR
tHD:DAT
tAA tDH
tSU:STO
tBUF
Symbol Table
WAVEFORM INPUTS
Must be steady
OUTPUTS
Will be steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes Allowed
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not Known
N/A Center Line is
High Impedance
5 FN6314.1
August 14, 2006
5 Page 
www.DataSheet4U.com
ISL1219
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the time base
for the RTC. Since the resonant frequency of a crystal is
temperature dependent, the RTC performance will also be
dependent upon temperature. The frequency deviation of
the crystal is a function of the turnover temperature of the
crystal from the crystal’s nominal frequency. For example, a
~20ppm frequency deviation translates into an accuracy of
~1 minute per month. These parameters are available from
the crystal manufacturer. The ISL1219 provides on-chip
crystal compensation networks to adjust load capacitance to
tune oscillator frequency from -94ppm to +140ppm. For
more detailed information see the Application Section.
Single Event and Interrupt
The alarm mode is enabled via the ALME bit. Choosing
single event or interrupt alarm mode is selected via the IM
bit. Note that when the frequency output function is enabled,
the alarm function is disabled.
The standard alarm allows for alarms of time, date, day of
the week, month, and year. When a time alarm occurs in
single event mode, an IRQ pin will be pulled low and the
alarm status bit (ALM) will be set to “1”.
The pulsed interrupt mode allows for repetitive or recurring
alarm functionality. Hence, once the alarm is set, the device
will continue to alarm for each occurring match of the alarm
and present time. Thus, it will alarm as often as every minute
(if only the nth second is set) or as infrequently as once a
year (if at least the nth month is set). During pulsed interrupt
mode, the IRQ pin will be pulled low for 250ms and the alarm
status bit (ALM) will be set to “1”.
The ALM bit can be reset by the user or cleared
automatically using the auto reset mode (see ARST bit).
The alarm function can be enabled/disabled during battery
backup mode using the FOBATB bit. For more information
on the alarm, please see the Alarm Registers Description.
Frequency Output Mode
The ISL1219 has the option to provide a frequency output
signal using the IRQ/FOUT pin. The frequency output mode
is set by using the FO bits to select 15 possible output
frequency values from 0 to 32kHz. The frequency output can
be enabled/disabled during battery backup mode using the
FOBATB bit.
General Purpose User SRAM
The ISL1219 provides 2 bytes of user SRAM. The SRAM will
continue to operate in battery backup mode. However, it
should be noted that the I2C bus is disabled in battery
backup mode.
I2C Serial Interface
The ISL1219 has an I2C serial bus interface that provides
access to the control and status registers and the user
SRAM. The I2C serial interface is compatible with other
industry I2C serial bus protocols using a bidirectional data
signal (SDA) and a clock signal (SCL).
Oscillator Compensation
The ISL1219 provides the option of timing correction due to
temperature variation of the crystal oscillator for either
manufacturing calibration or active calibration. The total
possible compensation is typically -94ppm to +140ppm. Two
compensation mechanisms that are available are as follows:
1. An analog trimming (ATR) register that can be used to
adjust individual on-chip digital capacitors for oscillator
capacitance trimming. The individual digital capacitor is
selectable from a range of 9pF to 40.5pF (based upon
32.758kHz). This translates to a calculated
compensation of approximately -34ppm to +80ppm. (See
ATR description.)
2. A digital trimming register (DTR) that can be used to
adjust the timing counter by ±60ppm. (See DTR
description.)
Also provided is the ability to adjust the crystal capacitance
when the ISL1219 switches from VDD to battery backup
mode. (See Battery Mode ATR Selection for more details.)
Register Descriptions
The battery-backed registers are accessible following a
slave byte of “1101111x” and reads or writes to addresses
[00h:19h]. The defined addresses and default values are
described in the Table 1. Address 09h is not used. Reads or
writes to 09h will not affect operation of the device but should
be avoided.
REGISTER ACCESS
The contents of the registers can be modified by performing
a byte or a page write operation directly to any register
address.
The registers are divided into 4 sections. These are:
1. Real Time Clock (7 bytes): Address 00h to 06h.
2. Control and Status (5 bytes): Address 07h to 0Bh.
3. Alarm (6 bytes): Address 0Ch to 11h.
4. User SRAM (2 bytes): Address 12h to 13h.
5. Time Stamp (6 bytes): Address 14h to 19h
There are no addresses above 19h.
Write capability is allowable into the RTC registers (00h to
06h) only when the WRTC bit (bit 4 of address 07h) is set to
“1”. A multi-byte read or write operation is limited to one
section per operation. Access to another section requires a
new operation. A read or write can begin at any address
within the section.
A register can be read by performing a random read at any
address at any time. This returns the contents of that register
location. Additional registers are read by performing a
sequential read. For the RTC and Alarm registers, the read
11 FN6314.1
August 14, 2006
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet ISL1219.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ISL1218 | I2C Real Time Clock/Calendar | Intersil Corporation |
| ISL1219 | Real Time Clock/Calendar | Intersil Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |