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PDF ATA5558 Data sheet ( Hoja de datos )
| Número de pieza | ATA5558 | |
| Descripción | 1 kbit R/W IDIC | |
| Fabricantes | ATMEL Corporation | |
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Features
• Contactless Read/Write Data Transmission
• Radio Frequency fRF:
100 kHz to 200 kHz
• User Memory (1024 Bits): 32 Write Protectable 32-bit Blocks of Data
• Deterministic Anticollision: Detection Rate ~ 20 Tags/s with 40-bit Tag ID, RF/32
• On-chip CRC Generator: 16-bit CRC-CCITT Compliant to ISO/IEC 11785
• Downlink Transmission: Enhanced 1 out of 4 Pulse Interval Encoding (~ 5 kbps)
• Uplink Transmission:
ASK Modulated, NRZ, Manchester or Bi-phase Encoding
• Integrated Tuning Capacitor: 75 pF ±10% as Mask Option
• System Memory (320 bits):
– 10 Write and Password Protectable 32 Bit Blocks of Data
– Tag ID (96 Bits Maximum)
– Traceability Data with Inherent Manufacturer Serial Number
– Write Password (32 Bits) and Read Password (32 Bits),
with Page Orientated Memory Protection Areas
– Configuration Register for Setup of:
• Selectable Data Bit Rate: RF/2 .. RF/64
• Selectable Tag ID Length to Optimize Anticollision Detection Rate
• Start of Frame with Variable Preamble Length to Simplify Interrogator Design
• Public Mode (PM) for Read Only Tag Emulation
• Electrical Article Surveillance (EAS) Mode
• Direct Data (NRZ), Bi-phase (FDX-B) or Manchester Data Encoding
1. General Description
The ATA5558 is a contactless, two-terminal R/W-Identification IC (IDIC®) for multi- or
single tag applications in the low frequency (≈ 125 kHz) range. The passive tag uses
the external RF signal to generate it’s own power supply and internal clock reference.
Figure 1-1. RFID System Using an ATA5558 Tag
Transponder
Reader or
BInateserrosgtaattioorn
Power
Data
Memory
*
ATA5558
1 kbit R/W IDIC®
with
Deterministic
Anticollision
ATA5558
Preliminary
* Mask option
It contains an EEPROM which is subdivided into 1024 bits of user memory and
320 bits of system memory. Both memory sections are organized in data blocks of
32 bits, each equipped with an associated lock bit for block write protection. The user
memory, which is intended for storage of recallable user data, is made of 32 such
blocks. The 10 block system memory section is reserved for system parameter and
configuration settings. Two of these blocks include a 32 bit read and a 32 bit write
password to prevent unauthorized read and/or write access to protected user defin-
able memory pages.
Rev. 4681C–RFID–09/05
1 page  
ATA5558 [Preliminary]
2.6.2
A valid Write command can be used for programming a data block of 33 bits – including the
associated lock bit – into an addressed location of either memory section. Once locked
(lock bit = 1), the entire block including the lock bit itself can no longer be reprogrammed
selectively.
The system memory section is situated at the upper end of the (6-bit) memory address range
and contains all system parameters and configuration settings. This area has restricted access
(see Figure 2-5 on page 7) and the majority of blocks can only be read or written after the suc-
cessful execution of the appropriate Password Login command (see Table 7-1 on page 24).
All the configuration settings are allocated in block 63 (see Figure 2-7 on page 9) and the pass-
word protection security information in block 62 (see Figure 2-6 on page 7).
Traceability Data
The traceability information is programmed and locked into the traceability blocks (59-61) by
Atmel during the production test.
Figure 2-4. Tag ID and Traceability Structure
Traceability
Block 61
Block 60
Block 59
Block 58
Block 57
Block 56
31 ................................. 16 15 ......... 8
IC code
ACL
wafer # 5bit
die on wafer 18 bit
LotID
30 .............. 26 25 ........................ 8
7 ............. 0
MFC
ICR LotID
7... 4 3 ... 0
TagID
TagID(msb-64).......TagID(msb-79) TagID(msb-80)........TagID(msb-95)
TagID(msb-32).......TagID(msb-48) TagID(msb-49)........TagID(msb-63)
TagID(msb)...........TagID(msb-16) TagID(msb-17)........TagID(msb-31)
31 ................... 16 15 ..................... 0
Anticollison detection starts with this bit
IC code
ACL
MFC
ICR
DPW
Wafer#
Lot ID
RFU
4-digit Atmel IC reference number, e.g. ’5558’
Allocation class as defined in ISO/IEC TDR 15963-1 = E0h
Manufacturer code of Atmel Corp. as defined in ISO/IEC 7816-6/AM1 = 15h
4-bit Atmel IC revision code
18-bit binary encoded die on wafer
5-bit binary wafer number
9-digit lot number
Reserved for Future Use
4681C–RFID–09/05
5
5 Page 
Figure 3-2. SOF Pattern
ATA5558 [Preliminary]
SOF
Example with
p = 4 bit periods
Preamble length = 3
2 bit period
code
violation
3.1.2
Public Mode
1. In Public Mode the cyclic data stream will be preceded by a single SOF pattern after the
completion of the POR delay.
2. The variable number of preamble data bits is aimed at easing the interrogator design
and optimizing system performance.
3. Within any closed identification system the preamble length for all tags must be
identical.
3.2 Interrogator to Tag Communication
All commands and data bit streams from the interrogator to the tag are 100% (OOK –
On-Off-Key) modulated using a modified 1 out of 4 pulse position coding. Depending on the
data, the continuous RF field is interspersed with short field gaps of constant duration and vari-
able separation. The time from one gap to the next may take on one of four discrete values.
Each of these represent one of four possible dual bit downlink data codes (00 .. 11) in the data
stream (see Figure 3-3). The downlink data transfer speed is dependent on the downlink data
rate (DDR) bit set in the tag configuration block, so that selected tags can always understand the
interrogator. The minimum write data coding (maximum data rate) is 9 field clocks. This corre-
sponds with the d00 (dref) parameter in Figure 3-3 and Table 3-1 on page 12.
Figure 3-3. Interrogator to Tag - Modified 1 out of 4 Pulse Position Coding
Uplink mode
Downlink mode
Sgap
d01 d11 d10
4681C–RFID–09/05
dref Wgap
d00
11
11 Page | ||
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| PDF Descargar | [ Datasheet ATA5558.PDF ] | |
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