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PDF ATAR510 Data sheet ( Hoja de datos )
| Número de pieza | ATAR510 | |
| Descripción | MARC 4 4-BIT UNIVERSAL MICROCONTROLLER | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Programmable System Clock with Prescaler and Five Different Clock Sources
– 4-MHz Crystal Oscillator
– 32-kHz Crystal Oscillator
– RC-oscillator Fully Integrated
– RC-oscillator with External Resistor Adjustment
– External Clock Input
• Wide Supply-voltage Range (2.2 V to 6.2 V)
• Very Low Halt Current (< 1 µA)
• 4-Kbyte ROM, 256 × 4-bit RAM
• 8 Hard and Software Interrupt Priority Levels
• Up to 10 External and 4 Internal Interrupts, Bit Wise Maskable with
Programmable Priority Level
• Up to 34 I/O Lines Including 8 High Drive I/O-lines (20 mA, VDD = 5 V)
• I/O Ports – Bit Wise Configurable with Combined Interrupt Handling
(for Serial I/O Applications)
• 2 × 8-bit Multifunction Timer/Counters
• Coded Reset and Watchdog Timer (Mask Option)
• Power-on Reset and “Brown Out” Function
• Various Power-down Modes
• Efficient, Hardware-controlled Interrupt Handling
• High Level Programming Language qFORTH
• Comprehensive Library of Useful Routines
• Windows® 95/Windows NT® Based Development Tools
MARC4 4-bit
Universal
Microcontroller
ATAR510
Description
The ATAR510 is a member of Atmel’s family of 4-bit single-chip microcontrollers. It
contains ROM, RAM, up to 34 digital I/O pins, up to 10 maskable external interrupt
sources, 4 maskable internal interrupts, a watchdog timer, interval timer, 2 x 8-bit mul-
tifunction timer/counter module, and a versatile software configurable on-chip system
clock module.
Rev. 4703B–4BMCU–01/05
1 page  
ATAR510
2. MARC4 Architecture
2.1 General Description
The MARC4 microcontroller consists of an advanced stack-based 4-bit CPU core and on-chip
peripherals. The CPU is based on the Harvard architecture with physically separate program
memory (ROM) and data memory (RAM). Three independent buses, the instruction bus, the
memory bus and the I/O bus, are used for parallel communication between ROM, RAM and
peripherals. This enhances program execution speed by allowing both instruction prefetching,
and a simultaneous communication to the on-chip peripheral circuitry. The extremely powerful
integrated interrupt controller with associated eight prioritized interrupt levels supports fast and
efficient processing of hardware events. The MARC4 is designed for the high-level programming
language qFORTH. The core includes both an expression and a return stack. This architecture
enables high-level language programming without any loss of efficiency or code density.
Figure 2-1. MARC4 Core
Reset
Reset
Clock
System
clock
Sleep
Program
memory
MARC4 CORE
X
PC Y
SP
RP
RAM
256 x 4-bit
Instruction
bus
Instruction
decoder
Interrupt
controller
I/O bus
Memory bus
CCR
TOS
ALU
On-chip peripheral modules
4703B–4BMCU–01/05
5
5 Page 
ATAR510
2.3.2
Interrupt Latency
The interrupt latency is the time from the occurrence of the interrupt to the interrupt service rou-
tine being activated. In MARC4 this is extremely short (taking between 3 to 5 machine cycles
depending on the state of the core).
Figure 2-6. Interrupt Handling
INT7
7 INT7 active
RTI
6 INT5
5 INT5 active
4 INT3
3 INT3 active
2
1
RTI
INT2
INT2 pending
SWI0
RTI
INT2 active
RTI
0
Main/
Autosleep
Time
INT0 pending
INT0 active
RTI
Main/
Autosleep
Table 2-1. Interrupt Priority Table
Interrupt
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
Priority
Lowest
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Highest
ROM Address
040h
080h
0C0h
100h
140h
180h
1C0h
1E0h
Maskable
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Interrupt Opcode
C8h (SCALL 040h)
D0h (SCALL 080h)
D8h (SCALL 0C0h)
E8h (SCALL 100h)
E8h (SCALL 140h)
F0h (SCALL 180h)
F8h (SCALL 1C0h)
FCh (SCALL 1E0h)
4703B–4BMCU–01/05
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ATAR510.PDF ] | |
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