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PDF AD9254 Data sheet ( Hoja de datos )
| Número de pieza | AD9254 | |
| Descripción | 14-Bit Analog to Digital Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR = 71.8 dBc (72.8 dBFS) to 70 MHz input
SFDR = 84 dBc to 70 MHz input
Low power: 430 mW @ 150 MSPS
Differential input with 650 MHz bandwidth
On-chip voltage reference and sample-and-hold amplifier
DNL = ±0.4 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary, Gray code, or twos complement data format
Clock duty cycle stabilizer
Data output clock
Serial port control
Built-in selectable digital test pattern generation
Programmable clock and data alignment
APPLICATIONS
Ultrasound equipment
IF sampling in communications receivers
CDMA2000, WCDMA, TD-SCDMA, and WiMax
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
Macro, micro, and pico cell infrastructure
GENERAL DESCRIPTION
The AD9254 is a monolithic, single 1.8 V supply, 14-bit, 150 MSPS
analog-to-digital converter (ADC), featuring a high performance
sample-and-hold amplifier (SHA) and on-chip voltage reference.
The product uses a multistage differential pipeline architecture
with output error correction logic to provide 14-bit accuracy at
150 MSPS data rates and guarantees no missing codes over the
full operating temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and offsets, including single-ended
applications. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling
single-channel inputs at frequencies well beyond the Nyquist rate.
Combined with power and cost savings over previously available
ADCs, the AD9254 is suitable for applications in communications,
imaging, and medical ultrasound.
A differential clock input controls all internal conversion cycles.
A duty cycle stabilizer (DCS) compensates for wide variations in
the clock duty cycle while maintaining excellent overall ADC
performance.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
14-Bit, 150 MSPS, 1.8 V
Analog-to-Digital Converter
AD9254
VIN+
VIN–
REFT
REFB
VREF
SENSE
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
AD9254
SHA
MDAC1
8-STAGE
1 1/2-BIT PIPELINE
A/D
4
A/D
8
3
CORRECTION LOGIC
15
OUTPUT BUFFERS
REF
SELECT
0.5V
CLOCK
DUTY CYCLE
STABILIZER
MODE
SELECT
OR
DCO
D13 (MSB)
D0 (LSB)
SCLK/DFS
SDIO/DCS
CSB
AGND
CLK+ CLK–
Figure 1.
PDWN DRGND
The digital output data is presented in offset binary, Gray code, or
twos complement formats. A data output clock (DCO) is provided
to ensure proper latch timing with receiving logic.
The AD9254 is available in a 48-lead LFCSP_VQ and is specified
over the industrial temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. The AD9254 operates from a single 1.8 V power supply
and features a separate digital output driver supply to
accommodate 1.8 V to 3.3 V logic families.
2. The patented SHA input maintains excellent performance
for input frequencies up to 225 MHz.
3. The clock DCS maintains overall ADC performance over a
wide range of clock pulse widths.
4. A standard serial port interface supports various product
features and functions, such as data formatting (offset
binary, twos complement, or Gray coding), enabling the
clock DCS, power-down, and voltage reference mode.
5. The AD9254 is pin-compatible with the AD9233, allowing
a simple migration from 12 bits to 14 bits.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
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AD9254
DIGITAL SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled,
unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Resistance
Input Capacitance
LOGIC INPUTS (SCLK/DFS, OEB, PWDN)
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Resistance
Input Capacitance
LOGIC INPUTS (CSB)
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Resistance
Input Capacitance
LOGIC INPUTS (SDIO/DCS)
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
DRVDD = 3.3 V
High Level Output Voltage (VOH, IOH = 50 μA)
High Level Output Voltage (VOH, IOH = 0.5 mA)
Low Level Output Voltage (VOL, IOL = 1.6 mA)
Low Level Output Voltage (VOL, IOL = 50 μA)
DRVDD = 1.8 V
High Level Output Voltage (VOH, IOH = 50 μA)
High Level Output Voltage (VOH, IOH = 0.5 mA)
Low Level Output Voltage (VOL, IOL = 1.6 mA)
Low Level Output Voltage (VOL, IOL = 50 μA)
Temperature Min
AD9254BCPZ-150
Typ Max
Unit
CMOS/LVDS/LVPECL
Full 1.2
V
Full 0.2
6 V p-p
Full AVDD − 0.3
AVDD + 1.6 V
Full 1.1
AVDD
V
Full 1.2
3.6 V
Full 0
0.8 V
Full −10
+10 μA
Full −10
+10 μA
Full 8 10
12 kΩ
Full 4
pF
Full 1.2
Full 0
Full −50
Full −10
Full 30
Full 2
3.6 V
0.8 V
−75 μA
+10 μA
kΩ
pF
Full 1.2
Full 0
Full −10
Full +40
Full 26
Full 2
3.6
0.8
+10
+135
V
V
μA
μA
kΩ
pF
Full 1.2
Full 0
Full −10
Full +40
Full 26
Full 5
DRVDD + 0.3
0.8
+10
+130
V
V
μA
μA
kΩ
pF
Full 3.29
Full 3.25
Full
Full
Full 1.79
Full 1.75
Full
Full
V
V
0.2 V
0.05 V
V
V
0.2 V
0.05 V
Rev. 0 | Page 5 of 40
5 Page 
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0
150MSPS
250.3MHz @ –1dBFS
–20
SNR = 69.3dBc (70.3dBFS)
ENOB = 11.3 BITS
SFDR = 79dBc
–40
–60
–80
–100
–120
0
18.75
37.50
56.25
FREQUENCY (MHz)
75.00
Figure 18. AD9254 Single-Tone FFT with fIN = 250.3 MHz
0
150MSPS
–20
ffIINN12
=
=
29.1MHz
32.1MHz
@
@
–7dBFS
–7dBFS
SFDR = 83.2dBc (90.2dBFS)
WoIMD3 = –83.9dBc (–90.9dBFS)
–40
–60
–80
–100
–120
0
18.75
37.50
56.25
FREQUENCY (MHz)
75.00
Figure 19. AD9254 Two-Tone FFT with fIN1 = 29.1 MHz, fIN2 = 32.1 MHz
90
SFDR –40°C
85
SFDR +25°C
80
75
SNR –40°C
70 SFDR +85°C
65
SNR +25°C SNR +85°C
60
0 50 100 150 200 250 300 350 400
INPUT FREQUENCY (MHz)
Figure 20. AD9254 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature with 2 V p-p Full Scale
AD9254
120
SFDR (dBFS)
100
80 SNR (dBFS)
60
40
SFDR (dBc)
20
85dBc
REFERENCE LINE
SNR (dBc)
0
–90 –80 –70 –60 –50 –40 –30 –20 –10
INPUT AMPLITUDE (dBFS)
0
Figure 21. AD9254 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 2.4 MHz
0
–20
SFDR (–dBc)
–40
WORST IMD3 (dBc)
–60
–80
–100
SFDR (–dBFS)
WORST IMD3 (dBFS)
–120
–90 –78 –66 –54 –42 –30 –18
INPUT AMPLITUDE (dBFS)
–6
Figure 22. AD9254 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 29.1 MHz, fIN2 = 32.1 MHz
90
SFDR +25°C
SFDR –40°C
85
80
SFDR +85°C
75
70
SNR +25°C
SNR –40°C
65
SNR +85°C
60
0 50 100 150 200 250 300 350 400
INPUT FREQUENCY (MHz)
Figure 23. AD9254 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature with 1 V p-p Full Scale
Rev. 0 | Page 11 of 40
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9254.PDF ] | |
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