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PDF ADF4108 Data sheet ( Hoja de datos )
| Número de pieza | ADF4108 | |
| Descripción | PLL Frequency Synthesizer | |
| Fabricantes | Analog Devices | |
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Data Sheet
PLL Frequency Synthesizer
ADF4108
FEATURES
GENERAL DESCRIPTION
8.0 GHz bandwidth
3.2 V to 3.6 V power supply
Separate charge pump supply (VP) allows extended tuning
voltage in 3.3 V systems
Programmable, dual-modulus prescaler
8/9, 16/17, 32/33, or 64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
Loop filter design possible with ADIsimPLL
4 mm × 4 mm, 20-lead chip scale package
APPLICATIONS
Broadband wireless access
Satellite systems
Instrumentation
Wireless LANs
Base stations for wireless radio
The ADF4108 frequency synthesizer can be used to implement
local oscillators in the upconversion and downconversion sections
of wireless receivers and transmitters. It consists of a low noise
digital PFD (phase frequency detector), a precision charge pump, a
programmable reference divider, programmable A and B counters,
and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B
(13-bit) counters, in conjunction with the dual-modulus prescaler
(P/P + 1), implement an N divider (N = BP + A). In addition,
the 14-bit reference counter (R counter), allows selectable REFIN
frequencies at the PFD input. A complete phase-locked loop (PLL)
can be implemented if the synthesizer is used with an external
loop filter and voltage controlled oscillator (VCO). Its very high
bandwidth means that frequency doublers can be eliminated in
many high frequency systems, simplifying system architecture
and reducing cost.
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD
VP CPGND
RSET
REFERENCE
REFIN
CLK
DATA
LE
RFINA
RFINB
14-BIT
R COUNTER
14
R COUNTER
LATCH
24-BIT INPUT
REGISTER
22
FUNCTION
LATCH
SDOUT
FROM
FUNCTION
LATCH
A, B COUNTER
LATCH
13
N = BP + A
13-BIT
B COUNTER
PRESCALER
P/P + 1
LOAD
LOAD
6-BIT
A COUNTER
CE AGND DGND
6
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
LOCK
DETECT
CURRENT
SETTING 1
CURRENT
SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
HIGH-Z
19 AVDD
MUX
MUXOUT
SDOUT
M3 M2 M1
ADF4108
Figure 1.
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2006–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADF4108
Data Sheet
Parameter
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
(PNSYNTH)9
Normalized 1/f Noise (PN1_f)10
Phase Noise Performance11
7900 MHz Output12
Spurious Signals
7900 MHz Output12
B Chips2
B Version1 (Typ)
Unit
−223
−122
−223
−122
dBc/Hz typ
dBc/Hz typ
−81 −81 dBc/Hz typ
−82 −82 dBc typ
Test Conditions/Comments
PLL loop B/W = 500 kHz, measured at 100 kHz offset
10 kHz offset; normalized to 1 GHz
@ VCO output
@ 1 kHz offset and 1 MHz PFD frequency
@ 1 MHz offset and 1 MHz PFD frequency
1 Operating temperature range (B version) is −40°C to +85°C.
2 The B chip specifications are given as typical values.
3 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
4 AVDD = DVDD = 3.3 V.
5 AC coupling ensures AVDD/2 bias.
6 Guaranteed by design. Sample tested to ensure compliance.
7 TA = 25°C; AVDD = DVDD = 3.3 V; P = 32; RFIN = 8 GHz, fPFD = 200 kHz, REFIN = 10 MHz.
8 TA = 25°C; AVDD = DVDD = 3.3 V; R = 16,383; A = 63; B = 891; P = 32; RFIN = 7.0 GHz.
9 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log FPFD. PNSYNTH = PNTOT − 10 log FPFD − 20 log N.
10 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF,
and at a frequency offset, f, is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). All phase noise measurements were performed with the EV-ADF4108EBZ1 and
the Agilent E5500 phase noise system. Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
11 The phase noise is measured with the EV-ADF4108EB1Z evaluation board, with the ZComm CRO8000Z VCO. The spectrum analyzer provides the REFIN for the
synthesizer (fREFOUT = 10 MHz @ 0 dBm).
12 fREFIN = 10 MHz; fPFD = 1 MHz; fRF = 7900 MHz; N = 7900; loop B/W = 30 kHz, VCO = ZComm CRO8000Z.
Rev. E | Page 4 of 20
5 Page 
ADF4108
PHASE FREQUENCY DETECTOR AND
CHARGE PUMP
The phase frequency detector (PFD) takes inputs from the R
counter and N counter (N = BP + A) and produces an output
proportional to the phase and frequency difference between
them. Figure 13 is a simplified schematic. The PFD includes a
programmable delay element that controls the width of the
antibacklash pulse. This pulse ensures that there is no dead zone
in the PFD transfer function and minimizes phase noise and
reference spurs. Two bits in the reference counter latch, ABP2
and ABP1, control the width of the pulse (see Figure 16). Use of
the minimum antibacklash pulse width is not recommended.
HI D1 Q1 UP
VP
CHARGE
PUMP
R DIVIDER
U1
CLR1
PROGRAMMABLE
DELAY
ABP2 ABP1
U3
CP
CLR2 DOWN
HI D2 Q2
N DIVIDER
U2
CPGND
Figure 13. PFD Simplified Schematic and Timing (in Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4108 allows the user to access
various internal points on the chip. The state of MUXOUT is
controlled by M3, M2, and M1 in the function latch. Figure 18
shows the full truth table. Figure 14 shows the MUXOUT section
in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect: digital
lock detect and analog lock detect.
Digital lock detect is active high. When the lock detect precision
(LDP) bit in the R counter latch is set to 0, digital lock detect is
set high when the phase error on three consecutive phase detector
(PD) cycles is less than 15 ns. With LDP set to 1, five consecutive
cycles of less than 15 ns are required to set the lock detect. It stays
set high until a phase error of greater than 25 ns is detected on any
subsequent PD cycle.
Data Sheet
The N-channel open-drain analog lock detect should be operated
with an external pull-up resistor of 10 kΩ nominal. When lock
has been detected, this output is high with narrow, low going
pulses.
DVDD
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
MUX
CONTROL
MUXOUT
Figure 14. MUXOUT Circuit
DGND
INPUT SHIFT REGISTER
The ADF4108 digital section includes a 24-bit input shift register, a
14-bit R counter, and a 19-bit N counter, comprising a 6-bit A
counter and a 13-bit B counter. Data is clocked into the 24-bit
shift register on each rising edge of CLK. The data is clocked in
MSB first. Data is transferred from the shift register to one of
four latches on the rising edge of LE. The destination latch is
determined by the state of the two control bits (C2, C1) in the
shift register. These are the 2 LSBs, DB1 and DB0, as shown in
the timing diagram of Figure 2. The truth table for these bits is
shown in Table 5.
Figure 15 shows a summary of how the latches are programmed.
Table 5. C2 and C1 Truth Table
Control Bits
C2 C1 Data Latch
0 0 R counter
0 1 N counter (A and B)
1 0 Function latch (including prescaler)
1 1 Initialization latch
Rev. E | Page 10 of 20
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet ADF4108.PDF ] | |
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