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PDF BL5372 Data sheet ( Hoja de datos )
| Número de pieza | BL5372 | |
| Descripción | Low-power real-time clock chip | |
| Fabricantes | SHANGHAI BELLING | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de BL5372 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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SHANGHAI
BELLING
BL5372
Low Power Real-Time Clock (RTC)
GENERAL DESCRIPTION
The BL5372 is a CMOS type real-time clock,
which is connected to the CPU via two wires
and capable of serial transmission of clock to
the CPU. The BL5372 can generate various
periodic interrupt clock pulses lasting for long
period (one month), and alarm interrupt can be
made by two incorporated systems. Since an
oscillation circuit is driven at a constant voltage,
it undergoes fluctuations of few voltage
and consequently offers low current
consumption (TYP. 400nA @ 5V)
It also provides an oscillator halt sensing
function applicable for data validation at
power-on and other occasions. The product
also incorporates a time trimming circuit that
adjusts the clock with higher precision by
adjusting any errors in crystal oscillator
frequencies based on signals from the CPU.
The crystal oscillator may be selected from
32KHz or 32.768KHz types.
It adopts 8-pin SOP or TSSOP package.
FEATURES
Lowest supply current: 400nA TYP. @ 5V
Connected to the CPU via only 2-wires
(MAX. 100KHz)
A clock counter (counting hours, minutes,
and seconds) and a calendar counter
(counting leap years, years, months, days,
and days of the week) in BCD codes
Two systems output providing interrupt to
the CPU output (period of one month to one
second, interrupt halt function)
Two systems output of alarm functions
Oscillation halt sensing to judge internal
data validity
Clock output of 32.768KHz (32KHz)
(output controllable via a register)
Second digit adjustment by ±30 seconds
Automatic leap year recognition up to the
year 2099
12-hour or 24-hour time display selectable
High precision time trimming circuit
Oscillator of 32.768KHz or 32KHz may be
used
CMOS logic
Package: 8pin SOP or TSSOP
BL5372 Data Sheet
1
1 page  
alarm may be selectable between on and
off for each day of the week, thus
allowing outputting alarm everyday or on
a specific day of the week. The
ALARM-A is output from the⎯INTRA
pin while the ALARM-B is output from
either the ⎯INTRA or the⎯INTRB pins.
Polling is possible separately for each
alarm function.
Periodic Interrupt:
The BL5372 can output periodic interrupt
pulses in addition to alarm function from
the ⎯INTRA and ⎯INTRB pins. This
frequency may be selected from 2Hz,
1Hz, 1/60Hz, 1/3600Hz and monthly by
controlling register (at lower 3 bits of
internal address EH) output selectively.
Output waveform for periodic interrupt may
be selected from regular pulse waveform
(2Hz and 1Hz) and waveforms (every second,
every minute, every hour and every month)
that are appropriate for CPU level
Shanghai Belling
interrupt.
Oscillation Halt Sensing
The oscillation halt sending function uses a
register (XSTP bit at internal address FH) to
store oscillation halt information. This
function may be used to determine if the BL
5372 supply power has been booted from
0V and if it has been backed up. This
function is useful for determining if clock
data is valid or invalid.
Clock Output
The BL5372 may output oscillation
frequency from INTRB pin. This clock
output is set for output by default, which is
set to on or off by setting the register
(internal address FH bit CLEN). It can also
choose different crystal oscillator
(32.768KHz or 32.000KHz) by setting the
register (internal address 7H at bit XSL),
and output clock pulses with two different
frequencies.
BL5372 Data Sheet
5
5 Page 
Shanghai Belling
3） When the time trimming circuit is used, periodic interrupt cycle changes every 20 seconds.
Pulse mode: “L” duration of output pulses may change in the maximum range of ±3.784ms
(±3.875ms when 32KHz crystal is used).
For example, Duty will be 50±0.3784% (or 50±0.3875% when 32KHz crystal
is used) at 1Hz.
Level Mode: Frequency is one second may change in the maximum range of ±3.784ms (±
3.875ms when 32KHz crystal is used).
Relation Between Mode Waveforms and CRFG Bit
Pulse mode
Level mode
CTFG
INTRA(INTRB)
CTFG=0
Second count-up
Second count-up
CTFG=0
Second count-up
7. Control Register 2 (at internal address FH)
D7 D6 D5 D4 D3 D2 D1 D0 Operation
-
-
12_/24
ADJ CLEN_ CTFG AAFG BAFG Write
0 0 12_/24 XSTP CLEN_ CTFG AAFG BAFG Read
0 0 Undefined 1 0 0 0 0 Default
*The default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage
drop, etc.
⎯12/24
⎯12/24-hour Time Display System Selection bit
⎯12/24
0
1
Description
12-hour time display system
24-hour time display system
Being set this bit at “0” indicates 12-hour display system while “1” indicates 24-hour system.
BL5372 Data Sheet
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet BL5372.PDF ] | |
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