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PDF ADV7392 Data sheet ( Hoja de datos )
| Número de pieza | ADV7392 | |
| Descripción | (ADV7390 - ADV7393) Low Power 10-Bit SD/HD Video Encoder | |
| Fabricantes | Analog Devices | |
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Hay una vista previa y un enlace de descarga de ADV7392 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Data Sheet
Low Power, Chip Scale,
10-Bit SD/HD Video Encoder
ADV7390/ADV7391/ADV7392/ADV7393
FEATURES
3 high quality, 10-bit video DACs
16× (216 MHz) DAC oversampling for SD
8× (216 MHz) DAC oversampling for ED
4× (297 MHz) DAC oversampling for HD
37 mA maximum DAC output current
Multiformat video input support
4:2:2 YCrCb (SD, ED, and HD)
4:4:4 RGB (SD)
Multiformat video output support
Composite (CVBS) and S-Video (Y-C)
Component YPrPb (SD, ED, and HD)
Component RGB (SD, ED, and HD)
Lead frame chip scale package (LFCSP) options
32-lead, 5 mm × 5 mm LFCSP
40-lead, 6 mm × 6 mm LFCSP
Wafer level chip scale package (WLCSP) option
30-ball, 5 × 6 WLCSP with single DAC output
Advanced power management
Patented content-dependent low power DAC operation
Automatic cable detection and DAC power-down
Individual DAC on/off control
Sleep mode with minimal power consumption
74.25 MHz 8-/10-/16-bit high definition input support
Compliant with SMPTE 274M (1080i), 296M (720p),
and 240M (1035i)
EIA/CEA-861B compliance support
NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support
NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz)
Macrovision Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant
Copy generation management system (CGMS)
Closed captioning and wide screen signaling (WSS)
Integrated subcarrier locking to external video source
Complete on-chip video timing generator
On-chip test pattern generation
Programmable features
Luma and chroma filter responses
Vertical blanking interval (VBI)
Subcarrier frequency (fSC) and phase
Luma delay
High definition (HD) programmable features
(720p/1080i/1035i)
4× oversampling (297 MHz)
Internal test pattern generator
Color and black bar, hatch, flat field/frame
Fully programmable YCrCb to RGB matrix
Gamma correction
Programmable adaptive filter control
Programmable sharpness filter control
CGMS (720p/1080i) and CGMS Type B (720p/1080i)
Dual data rate (DDR) input support
Enhanced definition (ED) programmable features
(525p/625p)
8× oversampling (216 MHz output)
Internal test pattern generator
Black bar, hatch, flat field/frame
Individual Y and PrPb output delay
Gamma correction
Programmable adaptive filter control
Fully programmable YCrCb to RGB matrix
Undershoot limiter
Macrovision Rev 1.2 (525p/625p) (ADV7390/ADV7392 only)
CGMS (525p/625p) and CGMS Type B (525p)
Dual data rate (DDR) input support
Standard definition (SD) programmable features
16× oversampling (216 MHz)
Internal test pattern generator
Color and black bar
Controlled edge rates for start and end of active video
Individual Y and PrPb output delay
Undershoot limiter
Gamma correction
Digital noise reduction (DNR)
Multiple chroma and luma filters
Luma-SSAF filter with programmable gain/attenuation
PrPb SSAF
Separate pedestal control on component and
composite/S-Video output
VCR FF/RW sync mode
Macrovision Rev 7.1.L1 (ADV7390/ADV7392 only)
Copy generation management system (CGMS)
Wide screen signaling (WSS)
Closed captioning
Serial MPU interface with I2C compatibility
2.7 V or 3.3 V analog operation
1.8 V digital operation
1.8 V or 3.3 V I/O operation
Temperature range: −40°C to +85°C
W Grade automotive range: −40°C to +105°C
Qualified for automotive applications
Rev. I
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2006–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
APPLICATIONS
Mobile handsets
Digital still cameras
Portable media and DVD players
Portable game consoles
Digital camcorders
Set-top box (STB)
Automotive infotainment (ADV7392 and ADV7393 only)
GENERAL DESCRIPTION
The ADV7390/ADV7391/ADV7392/ADV7393 are a family of
high speed, digital-to-analog video encoders on single monolithic
chips. Three 2.7 V/3.3 V, 10-bit video DACs (a single DAC for
the WLCSP package) provide support for composite (CVBS),
S-Video (Y-C), or component (YPrPb/RGB) analog outputs in
either standard definition (SD) or high definition (HD) video
formats. The single DAC WLCSP package supports CVBS
(NTSC and PAL) output only in SD resolution (see Table 2).
Optimized for low power operation, occupying a minimal
footprint, and requiring few external components, these
encoders are ideally suited to portable and power-sensitive
applications requiring TV-out functionality. Cable detection
and DAC autopower-down features ensure that power
consumption is kept to a minimum.
The ADV7390/ADV7391 have an 8-bit video input port that
supports SD video formats over an SDR interface and HD video
formats over a DDR interface. The ADV7392/ADV7393 have
a 16-bit video input port that can be configured in a variety of
ways. SD RGB input is supported.
All members of the family support embedded EAV/SAV timing
codes, external video synchronization signals, and the I2C® and
communication protocol. Table 1 and Table 2 list the video
standards directly supported by the ADV7390/ADV7391/
ADV7392/ADV7393 family.
ADV7390/ADV7391/ADV7392/ADV7393
Table 1. Standards Directly Supported by the LFCSP Packages
Active
Frame
Resolution I/P1 Rate (Hz)
Clock Input
(MHz)
Standard
720 × 240 P 59.94
27
720 × 288 P 50
27
720 × 480 I
29.97
27
ITU-R
BT.601/656
720 × 576 I
25
27
ITU-R
BT.601/656
640 × 480 I
29.97
24.54
NTSC Square
Pixel
768 × 576 I
25
29.5 PAL Square
Pixel
720 × 483 P 59.94
27
SMPTE 293M
720 × 483 P 59.94
27
BTA T-1004
720 × 483 P 59.94
27
ITU-R BT.1358
720 × 576 P 50
27
ITU-R BT.1358
720 × 483 P 59.94
27
ITU-R BT.1362
720 × 576 P 50
27
ITU-R BT.1362
1920 × 1035 I
30
74.25
SMPTE 240M
1920 × 1035 I
29.97
74.1758
SMPTE 240M
1280 × 720 P
60, 50, 30, 74.25
25, 24
SMPTE 296M
1280 × 720 P
23.97,
74.1758
59.94, 29.97
SMPTE 296M
1920 × 1080 I
30, 25
74.25
SMPTE 274M
1920 × 1080 I
29.97
74.1758
SMPTE 274M
1920 × 1080 P 30, 25, 24 74.25
SMPTE 274M
1920 × 1080 P 23.98, 29.97 74.1758
SMPTE 274M
1920 × 1080 P 24
74.25
ITU-R BT.709-5
1 I = interlaced, P = progressive.
Table 2. Standards Directly Supported by the WLCSP Package
Active
Frame
Resolution I/P1 Rate (Hz)
Clock Input
(MHz)
Standard
720 × 480 I
29.97
27
ITU-R
BT.601/656
720 × 576 I
25
27
ITU-R
BT.601/656
640 × 480 I
29.97
24.54
NTSC Square
Pixel
768 × 576 I
25
29.5 PAL Square
Pixel
1 I = interlaced, P = progressive.
Rev. I | Page 5 of 107
5 Page 
Data Sheet
ADV7390/ADV7391/ADV7392/ADV7393
VIDEO PERFORMANCE SPECIFICATIONS
VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, VDD_IO = 3.3 V, TA = +25°C.
Table 11.
Parameter
STATIC PERFORMANCE
Resolution
Integral Nonlinearity (INL)1
Differential Nonlinearity (DNL)1, 2
STANDARD DEFINTION (SD) MODE
Luminance Nonlinearity
Differential Gain
Differential Phase
Signal-to-Noise Ratio (SNR)3
ENHANCED DEFINITION (ED) MODE
Luma Bandwidth
Chroma Bandwidth
HIGH DEFINITION (HD) MODE
Luma Bandwidth
Chroma Bandwidth
Conditions
RSET = 510 Ω, RL = 37.5 Ω
RSET = 510 Ω, RL = 37.5 Ω
NTSC
NTSC
Luma ramp
Flat field full bandwidth
Min Typ Max Unit
10 Bits
0.5 LSBs
0.5 LSBs
0.5 ±%
0.5 %
0.6 Degrees
58 dB
75 dB
12.5 MHz
5.8 MHz
30.0
13.75
MHz
MHz
1 Measured on DAC 1, DAC 2, and DAC 3.
2 Differential nonlinearity (DNL) measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal
step value. For −ve DNL, the actual step value lies below the ideal step value.
3 Measured on the ADV7392/ADV7393 operating in 10-bit input mode.
POWER SPECIFICATIONS
VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, VDD_IO = 3.3 V, TA = +25°C.
Table 12.
Parameter
NORMAL POWER MODE1, 2
IDD3
IDD_IO
IAA 5
IPLL
SLEEP MODE
IDD
IAA
IDD_IO
IPLL
Conditions
Min Typ Max Unit
SD (16× oversampling enabled), CVBS (only one DAC turned on)
SD (16× oversampling enabled), YPrPb (three DACs turned on)
ED (8× oversampling enabled)4
HD (4× oversampling enabled)4
One DAC enabled
All DACs enabled
33 mA
68 mA
59 mA
81 101 mA
1 10 mA
50 mA
122 151 mA
4 10 mA
5 µA
0.3 µA
0.2 µA
0.1 µA
1 RSET = 510 Ω (all DACs operating in full-drive mode).
2 75% color bar test pattern applied to pixel data pins.
3 IDD is the continuous current required to drive the digital core.
4 Applicable to both single data rate (SDR) and dual data rate (DDR) input modes.
5 IAA is the total current required to supply all DACs.
Rev. I | Page 11 of 107
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADV7392.PDF ] | |
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