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PDF ZL50023 Data sheet ( Hoja de datos )
| Número de pieza | ZL50023 | |
| Descripción | Enhanced 4 K Digital Switch | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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ZL50023
Enhanced 4 K Digital Switch
Data Sheet
Features
• 4096 channel x 4096 channel non-blocking digital
Time Division Multiplex (TDM) switch at
8.192 Mbps and 16.384 Mbps or using a
combination of ports running at 2.048 Mbps,
4.096 Mbps, 8.192 Mbps and 16.384 Mbps
• 32 serial TDM input, 32 serial TDM output
streams
• Output streams can be configured as bi-
directional for connection to backplanes
• Exceptional input clock cycle to cycle variation
tolerance (20 ns for all rates)
• Per-stream input and output data rate conversion
selection at 2.048 Mbps, 4.096 Mbps 8.192 Mbps
or 16.384 Mbps. Input and output data rates can
differ
• Per-stream high impedance control outputs
(STOHZ) for 16 output streams
• Per-stream input bit delay with flexible sampling
point selection
October 2004
Ordering Information
ZL50023GAC 256-ball PBGA
ZL50023QCC 256-lead LQFP
-40°C to +85°C
• Per-stream output bit and fractional bit
advancement
• Per-channel ITU-T G.711 PCM A-Law/µ-Law
Translation
• Four frame pulse and four reference clock outputs
• Three programmable delayed frame pulse outputs
• Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz
• Input frame pulses: 61 ns, 122 ns, 244 ns
• Per-channel constant or variable throughput delay
for frame integrity and low latency applications
STi[31:0]
FPi
CKi
MODE_4M0
MODE_4M1
VDD_CORE
VDD_IO
VDD_COREA VDD_IOA
VSS
RESET
ODE
S/P Converter
Data Memory
P/S Converter
Input Timing
Connection Memory
Output HiZ
Control
Output Timing
STio[31:0]
STOHZ[15:0]
FPo[3:0]
CKo[3:0]
FPo_OFF[2:0]
Internal Registers &
Microprocessor Interface
Test Port
Figure 1 - ZL50023 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.
1 page  
ZL50023
Data Sheet
List of Tables
Table 1 - CKi and FPi Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2 - CKi and FPi Configurations for Divided Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3 - CKi and FPi Configurations for Multiplied Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4 - Output Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5 - Delay for Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 6 - Connection Memory Low After Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 7 - Connection Memory High After Block Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 8 - ZL50023 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 9 - Generated Output Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 10 - Input and Output Voice and Data Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 11 - Definition of the Four Quadrant Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 12 - Quadrant Frame Bit Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 13 - Address Map for Registers (A13 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 14 - Control Register (CR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 15 - Internal Mode Selection Register (IMS) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 16 - Software Reset Register (SRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 17 - Output Clock and Frame Pulse Control Register (OCFCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 18 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 19 - FPo_OFF[n] Register (FPo_OFF[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 20 - Internal Flag Register (IFR) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 21 - BER Error Flag Register 0 (BERFR0) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 22 - BER Error Flag Register 1 (BERFR1) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 23 - BER Receiver Lock Register 0 (BERLR0) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 24 - BER Receiver Lock Register 1 (BERLR1) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 25 - Stream Input Control Register 0 - 31 (SICR0 - 31) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 26 - Stream Input Quadrant Frame Register 0 - 31 (SIQFR0 - 31) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 27 - Stream Output Control Register 0 - 31 (SOCR0 - 31) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 28 - BER Receiver Start Register [n] (BRSR[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 29 - BER Receiver Length Register [n] (BRLR[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 30 - BER Receiver Control Register [n] (BRCR[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 31 - BER Receiver Error Register [n] (BRER[n]) Bits - Read Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 32 - Address Map for Memory Locations (A13 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 33 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 34 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 35 - Connection Memory High (CM_H) Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5
Zarlink Semiconductor Inc.
5 Page 
ZL50023
Data Sheet
PBGA Pin
Number
A8, A9, A14,
A15, E10,
M2, N2, P2,
P16, R2,
R16, T6, T7,
T8, T9, T10,
T11, T12,
T13, T14,
T15, D9, E8,
C8, E7, D6,
H5,P10, E9,
D8, B8, D7,
M14, R13
G15, G14,
E15, F14
H14, D11,
F15
B7, C7, B5,
J6
LQFP Pin
Number
61, 62,
63, 64,
65, 66,
67, 68,
134, 135,
136, 137,
138, 139,
140, 215,
219, 225,
229, 236,
237159,
163, 165,
167, 176,
221,43,
161, 164,
166, 168
46, 48
102, 106,
110, 112
100, 104,
108
170, 172,
174, 227
Pin Name
NC
MODE_4M0,
MODE_4M1
FPo0 - 3
FPo_OFF0 - 2
CKo0 - 3
Description
No Connect
These pins MUST be left unconnected.
4M Input Clock Mode 0 to 1 (5 V-Tolerant Input with internal
pull-down) These two pins should be tied together and are typically
used to select CKi = 4.096 MHz operation. See Table 8, “ZL50023
Operating Modes” on page 30 for a detailed explanation.
See Table 14, “Control Register (CR) Bits” on page 36 for CKi and FPi
selection using the CKIN1 - 0 bits.
ST-BUS/GCI-Bus Frame Pulse Outputs 0 to 3 (5 V-Tolerant
Three-state Outputs)
FPo0: 8 kHz frame pulse corresponding to the 4.096 MHz output
clock of CKo0.
FPo1: 8 kHz frame pulse corresponding to the 8.192 MHz output
clock of CKo1.
FPo2: 8 kHz frame pulse corresponding to 16.384 MHz output
clock of CKo2.
FPo3: Programmable 8 kHz frame pulse corresponding to
4.096 MHz, 8.192 MHz, 16.384 MHz, or 32.768 MHz output clock
of CKo3.
Generated Offset Frame Pulse Outputs 0 to 2 (5 V-Tolerant
Three-state Outputs)
Individually programmable 8 kHz frame pulses, offset from the
output frame boundary by a programmable number of channels.
ST-BUS/GCI-Bus Clock Outputs 0 to 3 (5 V-Tolerant
Three-state Outputs)
CKo0: 4.096 MHz output clock.
CKo1: 8.192 MHz output clock.
CKo2: 16.384 MHz output clock.
CKo3: 4.096 MHz, 8.192 MHz or 16.384 MHz programmable
output clock. 32.768 MHz if in multiplied clock mode.
11
Zarlink Semiconductor Inc.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ZL50023.PDF ] | |
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